Senior RTL Engineer

Eximietas Design; Pune District, Ahmedabad District, Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Eximietas Design in Bengaluru, Ahmedabad, Pune, and Hyderabad seeks an experienced ASIC RTL Design Engineer to join the team and drive RTL design, front-end flow and verification activities for next-generation SoC/IP solutions.

The candidate will work on Verilog/SystemVerilog, block/IP integration, lint/CDC, and timing/power optimization in a collaborative, multi-disciplinary environment.

Qualifications

• Bachelors degree in computer science, Electrical/Electronics Engineering, or a related field.
• Masters degree in computer science, Electrical/Electronics Engineering, or a related field.
• PhD in Computer Science, Electrical/Electronics Engineering, or a related field.
• Strong digital design fundamentals.
• Hands-on experience with ASIC flows EDA tools (DC, VCS/Xcelium, SpyGlass).
• Knowledge of bus protocols (AXI/AHB/PCIe/DDR).
• Scripting (Python/TCL) is a plus.

Responsibilities

• RTL design micro-architecture development (Verilog/System Verilog).
• End-to-end ASIC front-end flow: spec RTL synthesis STA support.
• Block/IP integration, lint/CDC, timing power optimization.
• Debugging, simulation, and cross-functional collaboration with DV/PD/DFT teams.

Skills

Verilog/SystemVerilog

Digital design fundamentals

Scripting (Python/TCL)

Education

Bachelors degree in Computer Science or Electrical/Electronics Engineering

Masters degree in Computer Science or Electrical/Electronics Engineering

PhD in Computer Science or Electrical/Electronics Engineering

Tools

DC

VCS/Xcelium

SpyGlass

Job description

Silicon Engineering / 4-10 Years

Senior RTL Engineer

Job Description

Senior RTL Engineer

Experience: 410 Years

Location: Bangalore / Ahmedabad / Pune /Hyderabad

Job Overview

We are looking for an experienced ASIC RTL Design Engineer to join our team and contribute to the design, development, and implementation of next-generation SoC/IP solutions.

Key Responsibilities

• RTL design micro-architecture development (Verilog/System Verilog)
• End-to-end ASIC front-end flow: spec RTL synthesis STA support
• Block/IP integration, lint/CDC, timing power optimization
• Debugging, simulation, and cross-functional collaboration with DV/PD/DFT teams

Qualifications Requirements

• Bachelors degree in computer science, Electrical/Electronics Engineering, or a related field. OR
• Masters degree in computer science, Electrical/Electronics Engineering, or a related field. OR
• PhD in Computer Science, Electrical/Electronics Engineering, or a related field.
• Strong digital design fundamentals
• Hands-on experience with ASIC flows EDA tools (DC, VCS/Xcelium, SpyGlass)
• Knowledge of bus protocols (AXI/AHB/PCIe/DDR)
• Scripting (Python/TCL) is a plus

Location - Bengaluru,Ahmedabad,Pune,Hyderabad