System-on-Chip Design Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru is seeking an accomplished ASIC/SoC RTL Designer to translate microarchitectures into high-performance RTL for next-generation AI, compute, and networking SoCs. You will collaborate with architecture, verification, DFT, STA, and physical design teams to deliver PPA-optimized RTL.

Responsibilities include designing datapaths, integrating AMBA interconnects, and driving RTL quality through linting, timing, and silicon bring-up.

Qualifications

• 5–12 years of ASIC/SoC RTL Design experience.
• Strong microarchitecture and RTL design expertise.
• Proficiency in Verilog/SystemVerilog and ARM-based SoC architecture.
• Experience with AMBA protocols, high-speed interfaces, and Synopsys Design Compiler.
• Hands-on with Lint, CDC/RDC, VCS/Xcelium/Questa, and Python/Tcl/Perl scripting.
• Exposure to advanced nodes (7nm/5nm/3nm) is a plus.

Responsibilities

• Develop microarchitecture and RTL using Verilog/SystemVerilog.
• Design datapaths, pipelines, FSMs, memory interfaces, and control logic.
• Integrate SoC IPs and AMBA-based interconnects (AXI/AHB/APB).
• Optimize designs for Power, Performance, and Area (PPA).
• Drive RTL quality through Lint, CDC/RDC, synthesis, and debug.
• Support timing closure, verification, and silicon bring-up.

Skills

ASIC/SoC RTL Design

Microarchitecture

Verilog/SystemVerilog

ARM-based SoC architecture

AMBA protocols

High-speed interfaces

Synopsys Design Compiler

Lint/CDC/RDC

Scripting (Python/Tcl/Perl)

7nm/5nm/3nm exposure

Tools

Synopsys Design Compiler

VCS/Xcelium/Questa

Job description

Design and implement high-performance SoC subsystems from microarchitecture to silicon. Collaborate with architecture, verification, DFT, STA, and physical design teams to deliver high-quality, PPA-optimized RTL for next-generation AI, Compute, and Networking SoCs.

Responsibilities

• Develop microarchitecture and RTL using Verilog/SystemVerilog.


• Design datapaths, pipelines, FSMs, memory interfaces, and control logic.


• Integrate SoC IPs and AMBA-based interconnects (AXI/AHB/APB).


• Optimize designs for Power, Performance, and Area (PPA).


• Drive RTL quality through Lint, CDC/RDC, synthesis, and debug.


• Support timing closure, verification, and silicon bring-up.

Required Skills

• 5–12 years of ASIC/SoC RTL Design experience.


• Strong microarchitecture and RTL design expertise.


• Proficiency in Verilog/SystemVerilog and ARM-based SoC architecture.


• Experience with AMBA protocols, high-speed interfaces, and Synopsys Design Compiler.


• Hands-on with Lint, CDC/RDC, VCS/Xcelium/Questa, and Python/Tcl/Perl scripting.


• Exposure to advanced nodes (7nm/5nm/3nm) is a plus.