Microarchitect & RTL Design Engineer

Baya Systems; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

Baya Systems is looking for a Microarchitect & RTL Design Engineer to develop advanced microarchitectures for configurable IPs in Bengaluru, India. The role requires over 8 years of experience in RTL development and expertise in Verilog and System Verilog. Candidates should be proficient in using industry-standard EDA tools, possess excellent problem-solving abilities, and demonstrate strong communication skills. This is an excellent opportunity to contribute to innovative technology solutions.

Qualifications

• 8+ years of hands-on experience in microarchitecture and RTL development.
• Familiarity with industry-standard EDA tools and methodologies.
• In-depth understanding of on-chip interconnects and NoCs.

Responsibilities

• Design and develop microarchitectures for configurable IPs.
• Collaborate with software teams to define configuration requirements.
• Work with verification teams on assertions and test plans.

Skills

Microarchitecture design

RTL coding

Verilog

System Verilog

Problem-solving skills

Strong communication skills

Education

BS, MS in Electrical Engineering, Computer Engineering or Computer Science

Tools

EDA tools

Python

Job description

Job Title: Microarchitect & RTL Design Engineer

About the Role: We are seeking a seasoned Microarchitect and RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Key Responsibilities

• Design and develop microarchitectures for a set of highly configurable IPs
• Microarchitecture and RTL coding ensuring optimal performance, power, area
• Collaborate with software teams to define configuration requirements, verification collaterals etc.
• Work with verification teams on assertions, test plans, debug, coverage etc.

Qualifications

• BS, MS in Electrical Engineering, Computer Engineering or Computer Science
• 8+ years and current hands‑on experience in microarchitecture and RTL development
• Proficiency in Verilog, System Verilog
• Familiarity with industry‑standard EDA tools and methodologies
• Experience with large high‑speed, pipelined, stateful designs, and low power designs
• In‑depth understanding of on‑chip interconnects and NoCs
• Experience within ARM ACE/CHI or similar coherency protocols
• Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NOCs
• Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus
• Experience with modern programming languages like Python is a plus
• Excellent problem‑solving skills and attention to detail
• Strong communication and collaboration skills