Silicon SoC Design Verification Engineer, HSIO

Google LLC; Bengaluru; On-site; INR 4,000,000 - 8,000,000; Full time

Job summary

Google LLC in Bengaluru seeks a senior Silicon SoC Design Verification Engineer, HSIO to lead verification strategy for high-speed interfaces across subsystems and the SoC. You will coordinate with design, architecture and post-silicon teams to ensure robust integration and performance.

The role requires a Bachelor's in a technical field and 8+ years in verification using C, SystemVerilog and UVM/OVM, plus hands-on experience with USB, PCIe, UFS, MIPI and HSIO PHY control.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
• 8 years of verification experience using C, SystemVerilog and OVM/UVM-based constrained random verification.
• Experience with high-speed protocols including USB2/USB3, PCIe, UFS, MIPI, and loopback concepts.

Responsibilities

• Lead HSIO PHY integration verification at Sub-system and SoC levels.
• Port HSIO PHY IP-level test cases to the SoC environment.
• Oversee RTL, GLS, and Timing regressions and HSIO VT simulations across RTL, GLS, Timing.
• Own testbench bring-up and integration of third-party VIP. Generate EVCD and bench collaterals.
• Deep waveform debugging and troubleshooting of complex digital design issues.

Skills

C

SystemVerilog

OVM/UVM

High-speed protocols

Testbench/verification

HSIO PHY

Education

Bachelor's degree in Electrical/Computer Engineering/CS

Master's degree (preferred)

Tools

Python

Perl

SKILL

Tcl

Job description

Silicon SoC Design Verification Engineer, HSIO

Share Silicon SoC Design Verification Engineer, HSIO

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience
• 8 years of experience in verification methodologies such as C, SystemVerilog and Open Verification Methodology/Universal Verification Methodology (OVM/UVM)-based constrained random verification.
• Experience of high-speed protocols including USB2/USB3, PCIe, UFS, MIPI, and in loopback test concepts.
• Experience with HSIO PHY Controllers and PHY+ controller test case porting.

Preferred qualifications:

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Strong understanding of SoC-level interfaces and the configurability of HSIO PHY registers.
• Experience leading verification modules or mentoring junior engineers in a complex SoC environment.
• Experience in scripting languages such as Python, Perl, SKILL, Tcl, or equivalent to build and automate verification flows.
• Track record of successfully taking complex mixed-signal/HSIO IP from the pre-silicon verification phase through to post-silicon validation.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a High-Speed Input/Output (HSIO) Physical Layer (PHY) Verification Lead at Google, you will play a critical role in the development of our next-generation custom silicon. You will lead the verification strategy and execution for high-speed interfaces, ensuring seamless integration and flawless performance at both the sub-system and SoC levels. You will collaborate closely with global, cross-functional teams spanning design, architecture, and post-silicon validation to drive our custom hardware from concept to successful silicon bring-up.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Lead HSIO PHY integration verification at both the Sub-system and SoC levels.
• Drive SoC-level test case development and successfully port HSIO PHY IP-level test cases to the SoC environment.
• Execute and oversee regressions in RTL, Gate-Level Simulations (GLS), and Timing simulations and perform HSIO PHY virtual tester (VT) simulations across RTL, GLS, and Timing environments.
• Own testbench bring-up, including the integration of third-party Verification IP (VIP).Generate EVCD and bench collaterals for target test cases to support downstream validation.
• Perform deep waveform debugging and troubleshoot complex digital design and verification issues.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.