Silicon SoC Integration Design Lead, Google Cloud

Google LLC; Bengaluru; Presencial; INR 6 000 000 - 9 000 000; Tempo integral

Resumo da oferta

Google LLC in Bengaluru is seeking a Silicon SoC Integration Design Lead for Google Cloud. You will guide a team of engineers across IPs and subsystems, shaping the microarchitecture and implementation of complex SoCs while collaborating with Architecture, Firmware, and Software teams to deliver high-performance silicon.

The role emphasizes leadership, design verification, timing and power analysis, and DFT experience.

Qualificações

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 10 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel.
• 5 years of experience in micro-architecture and design of SoCs and subsystems.
• 4 years of experience in people management, developing employees.
• Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Responsabilidades

• Lead SoC/SS integration team in Bengaluru design organization.
• Own microarchitecture and implementation of IPs and subsystems.
• Work with Architecture, Firmware and Software teams to drive feature closure and develop microarchitecture specifications.
• Drive design methodology, libraries, debug, code review in coordination with DV and physical design teams.
• Identify and drive Power, Performance and Area improvements for the domains owned.

Conhecimentos

ASIC leadership

Design verification

Microarchitecture

People management

DFT knowledge

Formação académica

Bachelor's degree in Electrical/Computer Engineering or related field

Ferramentas

Verilog/SystemVerilog

VHDL

Chisel

Descrição da oferta de emprego

Silicon SoC Integration Design Lead, Google Cloud

info_outline

info_outline X In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel.
• 5 years of experience in micro-architecture and design of SoCs and subsystems.
• 4 years of experience in people management, developing employees.
  
• Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience in SoC designs and integration flows.
• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
• Knowledge of high-performance and low power design techniques.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Lead SoC/SS integration team. Drive development of complex IPs and Subsystems along with a team of engineers in the Bengalurudesign organization.
• Own microarchitecture and implementation of IPs and subsystems.
• Work with Architecture, Firmware and Software teams to drive feature closure and develop microarchitecture specifications.
• Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
• Identify and drive Power, Performance and Area improvements for the domains owned.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

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