Design Verification Manager, Silicon

Google; Bengaluru; On-site; INR 6,000,000 - 9,000,000; Full time

Job summary

Google Bengaluru is seeking an experienced verification architect to lead comprehensive SoC verification efforts from pre-silicon through tape-out. You will mentor high-performing teams, drive pre-silicon emulation strategies using Palladium, Zebu, and SimXL, and collaborate with post-silicon validation to ensure robust silicon quality.

You will apply SystemVerilog, Verilog, and Python-based flows, with strong DV fundamentals and familiarity with DDR5/LPDDR5/HBM memory subsystems and JEDEC

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in front-end design or design verification.
• Experience in power-aware verification methodologies.
• Experience in fabric and interconnect architectures and cache coherency protocols.

Responsibilities

• Lead and manage comprehensive verification activities for complex System-on-Chip (SoC) architectures, ensuring robust quality standards from pre-silicon to tape-out.
• Manage and mentor high-performing engineering teams, driving execution, fostering a culture of technical excellence, and supporting career growth.
• Drive SoC-level pre-silicon emulation strategies (e.g., Palladium, Zebu, SimXL) to accelerate hardware-software co-verification, boot operating systems, and catch complex system-level bugs early.
• Oversee complex post-silicon debug activities, collaborating closely with post-silicon validation teams to root-cause silicon issues, bring up hardware, and correlate pre-silicon verification coverage with actual silicon behavior.
• Develop and scale aspects of logic verification infrastructure and advanced methodologies across the SoC, maintaining strong integration standards with architecture, design, and cross-functional teams.

Skills

SystemVerilog

Verilog

Python

Perl

UVM

SoC verification

Pre-silicon emulation

Hardware design knowledge

Team leadership

Memory subsystem verification

Education

Bachelor's degree in Electrical Engineering, Computer Science, or equivalent

Master's degree in Electrical Engineering or Computer Science or equivalent

Tools

Palladium

Zebu

SimXL

Formal verification

Portable Stimulus (PSS)

Job description

In most instances, this position requires in-person interviews as part of the hiring process.Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in front-end design or design verification.
• Experience in power-aware verification methodologies.
• Experience in fabric and interconnect architectures and cache coherency protocols.
  

Preferred qualifications:

• Master's degree in Electrical Engineering or Computer Science or equivalent practical experience.
• Experience in verification of high-bandwidth memory subsystems (DDR5, LPDDR5, HBM) including physical layer (PHY) training, memory controllers, and JEDEC compliance.
• Extensive experience directly managing high-performing engineering teams with a proven track record of successfully delivering complex, production-grade SoCs.
• Technical expertise in SoC-level verification and strong design verification (DV) fundamentals using universal verification methodology (UVM)-based environments. Direct Experience with pre-silicon emulation platforms and hardware accelerators (e.g., SimXL, formal verification, or portable stimulus standard/PSS).
• Strong programming skills in SystemVerilog, Verilog, and scripting languages like Python or Perl.
  

About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities

• Lead and manage comprehensive verification activities for complex System-on-Chip (SoC) architectures, ensuring robust quality standards from pre-silicon to tape-out.
• Manage and mentor high-performing engineering teams, driving execution, fostering a culture of technical excellence, and supporting career growth.
• Drive SoC-level pre-silicon emulation strategies (e.g., Palladium, Zebu, SimXL) to accelerate hardware-software co-verification, boot operating systems, and catch complex system-level bugs early.
• Oversee complex post-silicon debug activities, collaborating closely with post-silicon validation teams to root-cause silicon issues, bring up hardware, and correlate pre-silicon verification coverage with actual silicon behavior.
• Develop and scale aspects of logic verification infrastructure and advanced methodologies across the SoC, maintaining strong integration standards with architecture, design, and cross-functional teams.
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .