Senior Silicon Physical Design Engineer, Google Cloud

Google LLC; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

Google LLC in Bengaluru seeks a Senior Silicon Physical Design Engineer for Google Cloud. You will push boundaries in custom silicon, delivering high-performance, energy-efficient hardware for consumer-focused products and scalable cloud infrastructure.

You will collaborate with DFT, architecture, and packaging teams, solving complex problems with innovative micro-architecture and practical circuit design choices to optimize performance, power, and area.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with advanced design, including clock/voltage domain crossing, design for testing (DFT), and low power designs.
• Experience with system on a chip (SoC) cycles.
• Experience in high-performance, high-frequency, and low-power designs.

Responsibilities

• Define and drive the implementation of physical design methodologies.
• Take ownership of one or more physical design partitions or top level.
• Manage timing and power consumption of the design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design related rule sets for the functional design engineers.

Skills

Advanced silicon design

Clock/Voltage domain crossing

DFT

Low power design

SoC cycles

Education

Bachelor's degree in Electrical/CS/related field

Tools

SystemVerilog

TCL scripting

Layout verification

VLSI design

Job description

Senior Silicon Physical Design Engineer, Google Cloud

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• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with advanced design, including clock/voltage domain crossing, design for testing (DFT), and low power designs.
• Experience with system on a chip (SoC) cycles.
• Experience in high-performance, high-frequency, and low-power designs.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in coding with System Verilog and scripting with TCL.
• Experience with layout verification and design rules.
• Experience with very large scale integration (VLSI) design in SoC or multiple-cycles of SoC in ASIC design.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Physical Design Engineer, you will collaborate closely with the functional design, Design For Testing (DFT), architecture, and packaging engineers. Additionally, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Define and drive the implementation of physical design methodologies.
• Take ownership of one or more physical design partitions or top level.
• Manage timing and power consumption of the design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design related rule sets for the functional design engineers.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.