CPU Design Verification Engineer, Core IP

Google LLC; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

Google LLC is seeking a CPU Design Verification Engineer, Core IP to verify next‑gen RISC‑V processor cores, architectures and related peripherals. You will design verification infrastructure, testbenches and metrics to ensure high‑quality DV sign‑off.

You will collaborate with design and architecture teams, build constrained-random environments using SystemVerilog and UVM, and drive verification plans from pre‑to post‑silicon bring‑up in a fast‑paced product area.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 10 years of experience in verification of IPs, Subsystems and SoCs.
• 8 years of experience in creating design verification strategies and plans, constraint random verification with SystemVerilog (SV) and Universal Verification Methodology (UVM).
• 8 years of experience in verifying multi-stage, high-performance CPU core and related peripherals, RISC-V architecture and ISA extensions.

Responsibilities

• Work with designers, architects and other stakeholders to come up with detailed test plans, dependencies and deliverables.
• Plan the verification of RISC V CPU cores and related peripherals by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
• Work closely with Architecture, software, design stakeholders to make technical decisions. Create and enhance constrained-random verification environments using System Verilog and UVM. Represent DV status throughout the development process.
• Take technical decisions independently and ensure momentum for the project. Set the goal and own IP verification methodology. Identify methodology improvements.
• Partner with Pre-Silicon (Si) and Post-Si Validation teams for successful bring up of the IP.

Skills

IP verification

SystemVerilog

UVM

RISC-V architecture

ISA extensions verification

Education

Bachelor's degree in EE/CE/CS

Master's or PhD (preferred) in EE/CE/CS

Tools

SystemVerilog

UVM

Job description

CPU Design Verification Engineer, Core IP

Share CPU Design Verification Engineer, Core IP

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in verification of IPs, Subsystems and SoCs.
• 8 years of experience in creating design verification strategies and plans, constraint random verification with SystemVerilog (SV) and Universal Verification Methodology (UVM).
• 8 years of experience in verifying multi-stage, high-performance CPU core and related peripherals, RISC-V architecture and ISA extensions.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with low power, debug, performance verification and use cases verification.
• Experience with Security IP and subsystems.
• Familiarity with scripting languages (Python, Perl, or Tcl).
• Interest in AI-assisted IP Verification Methodologies.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Design Verification Engineer, you will be a key member of the team responsible for Verifying our next-generation RISC-V processor cores. In this role, you will focus on verifying architecture features, including standard or custom RISC-V Instruction Set Architecture (ISA) extensions. You will leverage your deep expertise in verifying CPU Architecture and ensure high quality Design Verification (DV) sign-off. This includes building verification infrastructure, testbenches, planning, metrics development and convergence of metrics to deliver high quality CPU cores and related peripherals.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Design Verification Engineer, you will be a key member of the team responsible for Verifying our next-generation RISC-V processor cores. In this role, you will focus on verifying architecture features, including standard or custom RISC-V Instruction Set Architecture (ISA) extensions. You will leverage your deep expertise in verifying CPU Architecture and ensure high quality Design Verification (DV) sign-off. This includes building verification infrastructure, testbenches, planning, metrics development and convergence of metrics to deliver high quality CPU cores and related peripherals.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Work with designers, architects and other stakeholders to come up with detailed test plans, dependencies and deliverables.
• Plan the verification of RISC V CPU cores and related peripherals by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
• Work closely with Architecture, software, design stakeholders to make technical decisions. Create and enhance constrained-random verification environments using System Verilog and UVM. Represent DV status throughout the development process.
• Take technical decisions independently and ensure momentum for the project. Set the goal and own IP verification methodology. Identify methodology improvements.
• Partner with Pre-Silicon (Si) and Post-Si Validation teams for successful bring up of the IP.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.