Silicon SoC Analog Integration Lead, Google Cloud

Google; Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Google is seeking an SoC Analog Integration Lead in Bengaluru to drive strategy, selection, and architectural/physical integration of high-speed analog/mixed-signal IPs (PCIe, SerDes, DDR, HBM PHY) into complex SoCs. You’ll manage external/internal IP providers and collaborate with floorplan, packaging, and validation teams across the full development lifecycle.

You will own the silicon integration lifecycle, ensuring performance, power, thermal, area, and signal integrity meet strict

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 10 years of experience in analog and mixed-signal IPs (PCIe, UCIe, Serdes, HBM, DDR PHYs) in advanced tech nodes.
• Experience negotiating specs and managing deliverables with IP vendors.

Responsibilities

• Lead evaluation and selection of third-party analog/mixed-signal IPs with detailed SLAs & delivery schedules.
• Serve as primary technical interface to IP vendors, oversee reviews, bug tracking, silicon errata evaluations.
• Collaborate with floorplan and physical design to define integration requirements (placement, power, clocking).
• Partner with packaging, PCB, and SI teams to optimize high-speed traces and die-package co-design.
• Oversee AMS simulations, post-silicon bring-up, lab characterization and validation for ramp to production.

Skills

Analog/mixed-signal IPs

Technical vendor management

IP evaluation & integration

Education

Bachelor's degree in EE/CS

Master's/PhD in EE/CS (preferred)

Job description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in analog and mixed-signal IPs such as PCIe, UCIe, Serdes, HBM or DDR PHYs in advanced technology nodes.
• Experience negotiating technical specifications and managing technical deliverables with IP vendors.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience across architectural requirements, physical design, packaging and board constraints and system considerations for high speed IO and memory PHYs.
• Experience planning or utilizing DFT hooks and on-chip telemetry to support silicon health monitoring and bring-up workflows.
• Track record of successfully integrating complex Ios and mixed signal IPs into an SoC and experience in post-Si taking SoCs to production quality.
• Proven expertise managing end-to-end technical evaluations, performance assessment, and QA sign-offs with third-party analog IP vendors.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As the SoC Analog Integration Lead, you will play a critical role in driving the strategy, selection, architectural and physical integration, and silicon execution of high-speed analog and mixed-signal IPs— including PCIe, SerDes, DDR, HBM PHY etc—into complex, high-performance SoCs.

In this role, you will engage with external and internal IP providers, SoC architects, package/board engineering teams, physical design, timing and floorplan teams and post-silicon validation teams. You will own the full life cycle of analog IP integration, ensuring that strict performance, power, thermal, area, floorplan, signal integrity, and system-level interface requirements are met from early architecture through volume production.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Lead the evaluation and selection of third-party analog/mixed-signal IPs (e.g., PCIe, SerDes, HBM PHY), establishing detailed technical SLAs, functional specifications, and delivery schedules.
• Serve as the primary technical interface to IP vendors, overseeing technical reviews, bug tracking, silicon errata evaluations, and waiver processes.
• Collaborate with floorplan and physical design teams to define integration requirements, ensuring alignment on placement, power delivery, clocking, and functional interfaces.
• Partner with packaging, PCB, and SI teams to optimize high-speed trace and power delivery, driving the die-package co-design process.
• Oversee AMS simulations and netlist checks, while leading post-silicon bring-up, lab characterization (BER, jitter), and validation to support the product ramp.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .