Silicon Micro-architecture Design Lead, Google Cloud

Google; Bengaluru; On-site; INR 5,000,000 - 9,000,000; Full time

Job summary

Google is hiring for a senior ASIC/SoC role in Bengaluru to advance custom silicon powering Google’s ML workloads.

You will work on IP/Subsystem design, micro-architecture, and industrial-grade verification to deliver high-performance accelerators for data centers.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in ASIC/SoC development with Verilog/SystemVerilog.
• Experience in micro-architecture and design of IPs and Subsystems.
• Experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Responsibilities

• Lead a team of Engineers in the design organization to deliver complex IPs or Subsystems.
• Define micro-architecture (uArch) specifications and block-level design documents, including interface protocols, block diagrams, transaction flows, and pipeline details.
• Perform RTL development, subsystem integration, and SoC integration, as well as Lint, CDC, FV, and UPF checks.
• Participate in simulation debug, synthesis, timing and power closure, and silicon bring-up.
• Participate in test plan and coverage analysis of the block and SOC-level verification.

Skills

ASIC/SoC development

Verilog/SystemVerilog

micro-architecture

IP/Subsystem design

design verification

DFT

Python/Perl

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Master's or PhD in Electrical/Computer Engineering or CS (preferred)

Tools

Python

Perl

Job description

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in ASIC/SoC development with Verilog/SystemVerilog.
• Experience in micro-architecture and design of IPs and Subsystems.
• Experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in ASIC/SoC development with Verilog/SystemVerilog.
• Experience in micro-architecture and design of IPs and Subsystems.
• Experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
• Experience with coding languages (e.g., Python or Perl).
• Experience in System on a Chip (SoC) designs and integration flows.
• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
• Knowledge of high-performance and low-power design techniques.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will join a team developing Application-Specific Integrated Circuits (ASICs) to accelerate machine learning computation in data centers. You will collaborate with Architecture, Verification, Power and Performance, and Physical Design teams to specify and deliver quality designs for next-generation accelerators. You will solve technical problems through micro-architecture innovation and evaluate design trade-offs between performance and power.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Lead a team of Engineers in the design organization to deliver complex IPs or Subsystems. Communicate and work with multi-disciplined and multi-site teams.
• Define micro-architecture (uArch) specifications and block-level design documents, including interface protocols, block diagrams, transaction flows, and pipeline details.
• Perform RTL development, subsystem integration, and System on a Chip (SoC) integration, as well as Lint, CDC, FV, and UPF checks.
• Participate in simulation debug, synthesis, timing and power closure, and silicon bring-up.
• Participate in test plan and coverage analysis of the block and SOC-level verification.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.