Silicon Physical Design STA Lead, Google Cloud

Google LLC; Bengaluru; Hybrid; INR 4,200,000 - 7,000,000; Full time

Job summary

Google LLC's Google Cloud division seeks a Silicon Physical Design STA Lead to drive timing and power convergence for SoC blocks and subsystems used in data-center accelerators. You will lead a team, collaborate with architecture, verification, power and performance, and define STA constraints for physical design engineers.

Be part of an effort delivering high-performance, low-power silicon with scalable methodologies.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or CS required.
• 10 years of advanced design experience including clock/voltage domain crossing, DFT, and low power designs.
• 6 years of people management experience and employee development.

Responsibilities

• Lead a team of individuals, set and communicate priorities, provide feedback and coaching.
• Drive to the closure of timing and power consumption of the design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design STA constraints for engineers.

Skills

Leadership and people management

STA

SoC/ASIC design

High-frequency/low-power design

Team mentorship

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Tools

TCL scripting

Perl/Python scripting

VLSI design tooling

Job description

Silicon Physical Design STA Lead, Google Cloud

In most instances, this position requires in-person interviews as part of the hiring process.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.
• 6 years of experience in people management, developing employees.
  
• Experience with Static Timing Analysis (STA) convergence on blocks, Subsystem (SS) or SoC.
• Experience with System on a Chip (SoC) cycles.
• Experience in high-performance, high-frequency, and low-power designs.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with scripting languages such as Perl, Python, or Tcl.
  
• Experience in Very-Large-Scale Integration (VLSI) design in SoC or experience with multiple-cycles of SoC in ASIC design.
• Experience in coding constraints and scripting with TCL.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

Responsibilities

• Lead a team of individuals, set and communicate individual and team priorities that support organizational goals. Meet regularly with individuals to discuss performance and development, and provide feedback and coaching. Take ownership of Static Timing Analysis (STA) of one or more physical design partitions and top level.
• Drive to the closure of timing and power consumption of the design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design STA constraints rule sets for the physical design engineers.