Senior Silicon Physical Design Engineer, Google Cloud

Google; Bengaluru; Presencial; INR 4 000 000 - 8 000 000; Tempo integral

Resumo da oferta

Google in Bengaluru is seeking a Senior Physical Design Engineer to shape next‑generation hardware, delivering high-performance, energy-efficient silicon for AI and data center products.

You will collaborate with design, DFT, and packaging teams to optimize micro-architecture and logic circuits, balancing performance, power, and area while applying scalable physical design methodologies across TPUs and SoC projects.

Qualificações

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience with advanced design, including clock/voltage domain crossing, design for testing (DFT), and low power designs.
• Experience with system on a chip (SoC) cycles.
• Experience in high-performance, high-frequency, and low-power designs.

Responsabilidades

• Define and drive the implementation of physical design methodologies.
• Take ownership of one or more physical design partitions or top level.
• Manage timing and power consumption of the design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design related rule sets for the functional design engineers.

Conhecimentos

Advanced design

Clock domain crossing

DFT

Low power design

SoC cycles

High-frequency design

SystemVerilog

TCL scripting

Layout verification

Formação académica

Bachelor's degree in Electrical Engineering/Computer Engineering/Computer Science or related field

Equivalent practical experience

Master’s degree or PhD in Electrical/Computer Engineering or CS (emphasis on computer architecture)

Ferramentas

SystemVerilog

TCL scripting

Descrição da oferta de emprego

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with advanced design, including clock/voltage domain crossing, design for testing (DFT), and low power designs.
• Experience with system on a chip (SoC) cycles.
• Experience in high-performance, high-frequency, and low-power designs.

Preferred qualifications

• Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in coding with System Verilog and scripting with TCL.
• Experience with layout verification and design rules.
• Experience with very large scale integration (VLSI) design in SoC or multiple-cycles of SoC in ASIC design.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct-to-consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Physical Design Engineer, you will collaborate closely with the functional design, Design For Testing (DFT), architecture, and packaging engineers. Additionally, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We’re the driving force behind Google’s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Define and drive the implementation of physical design methodologies.
• Take ownership of one or more physical design partitions or top level.
• Manage timing and power consumption of the design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design related rule sets for the functional design engineers.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.