Senior/ Staff Memory Layout Engineer

Prodapt ASIC services (Formerly Innovative Logic); Bengaluru; On-site; INR 2,400,000 - 4,200,000; Full time

Job summary

Prodapt ASIC services (Formerly Innovative Logic) is seeking a Memory Layout Engineer to drive custom layout design for memory blocks in a cutting-edge FinFET environment. You will collaborate with circuit design teams to hit performance, area, and reliability targets.

The role requires 4+ years in memory layout, proficiency with Cadence Virtuoso and Calibre/Assura, and hands-on experience with 2nm–7nm TSMC processes. A Bachelors or Masters in Electronics Engineering is expected.

Qualifications

• Experience: 4+ years in Memory Layout design.
• Technical Skills: Cadence Virtuoso and Calibre/Assura.
• Node Expertise: 2nm to 7nm TSMC processes.
• Education: Bachelor’s or Master’s degree in Electronics Engineering or a related field.

Responsibilities

• Design custom layouts for memory blocks including SRAM, DRAM, ROM, and Register Files.
• Execute and verify DRC/LVS checks and parasitic extraction.
• Optimize layouts for area and performance in collaboration with circuit designers.
• Apply expertise in deep submicron and FinFET technologies.

Skills

Memory layout design

SRAM

DRAM

ROM

Register Files

DRC/LVS

Parasitic extraction

FinFET

Education

Bachelor’s or Master’s degree in Electronics Engineering

Tools

Cadence Virtuoso

Calibre/Assura

Job description

The Role

We are seeking a Memory Layout Engineer to drive the custom layout design of memory blocks. You will collaborate with circuit design teams to ensure performance, area, and reliability targets are met using the latest FinFET technologies.

Key Responsibilities

• Design custom layouts for memory blocks including SRAM, DRAM, ROM, and Register Files.
• Execute and verify DRC/LVS checks and parasitic extraction.
• Optimize layouts for area and performance in collaboration with circuit designers.
• Apply expertise in deep submicron and FinFET technologies.

Required Qualifications

• Experience: 4+ years in Memory Layout design
• Technical Skills: Mastery of Cadence Virtuoso and Calibre/Assura
• Node Expertise: Hands-on experience with 2nm to 7nm TSMC processes
• Education: Bachelor’s or Master’s degree in Electronics Engineering or a related field