Memory Layout Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd in Bengaluru is seeking an experienced Memory Layout Engineer to design memory layouts for advanced semiconductor blocks and to integrate top-level layouts.

You will perform physical verification with DRC and LVS, ensure DFx/DFY requirements, and develop automation scripts using PERL, Shell, TCL, or SKILL.

4+ years of relevant experience and strong knowledge of memory layout for 2nm/3nm/5nm process nodes are preferred.

Qualifications

• 4+ years of memory layout engineering experience.
• Experience with 2nm/3nm/5nm process technologies.

Responsibilities

• Design memory layouts for building blocks (Bit Cell Arrays, Row/Column Decoders, Sense Amplifiers, I/O blocks).
• Integrate top-level memory layouts.
• Perform physical verification using DRC and LVS.
• Ensure layouts comply with DFM and DFY requirements.
• Analyze layouts for power integrity and signal integrity.
• Develop and maintain automation scripts using PERL, Shell, TCL, or SKILL.

Skills

Memory Layout

Physical verification

Power/Signal integrity

Automation scripting

Job description

We’re Hiring | Memory Layout Engineers

We’re looking for experienced Memory Layout Engineers to join our team and work on cutting-edge semiconductor technologies.

Experience:

4+ Years

Key Responsibilities:

• Design memory layouts for various building blocks, including:
• Bit Cell Arrays ,Row Decoders, Column Decoders, Sense Amplifiers, Input/Output (I/O) Blocks
• Integrate top-level memory layouts.
• Perform physical verification using DRC and LVS.
• Ensure layouts comply with Design for Manufacturability (DFM) and Design for Yield (DFY) requirements.
• Analyze layouts for power integrity and signal integrity.
• Develop and maintain automation scripts using PERL, Shell, TCL, or SKILL.

Required Skills:

• Strong hands-on experience in Memory Layout for advanced technology nodes.
• Expertise in TSMC and/or other process technologies with lower nodes (2nm/3nm/5nm).
• Solid understanding of physical verification, layout methodologies, and semiconductor design flows.
• Scripting knowledge is an added advantage.