Memory Layout Engineer: Bangalore

Incise Infotech; Bengaluru; On-site; INR 4,500,000 - 7,000,000; Full time

Job summary

Incise Infotech in Bengaluru seeks an experienced Memory Layout Engineer to drive custom layout design, memory leafcell layout libraries, and top-level integration. You will apply FinFET-aware techniques to optimize performance and area while ensuring robust physical verification readiness.

Candidates should have hands-on experience with DRC, LVS, ERC, and boundary checks, and a strong track record resolving complex layout issues.

Qualifications

• Hands-on experience in Memory Layout and Custom Layout Design.
• Experience building Memory Leafcell Layout Libraries and top-level integration.
• Understanding of memory architectures and layout structures.
• Proficiency in FinFET technology and advanced process nodes.
• Knowledge of FinFET layout design rules and process constraints.
• Experience with Physical Verification flow: DRC, LVS, ERC, and boundary checks.
• Ability to analyze and resolve complex layout issues.

Responsibilities

• Design memory layouts and optimize for area and performance.
• Develop and integrate memory leafcell libraries at top level.
• Apply FinFET-aware layout techniques.
• Perform physical verification and debugging (DRC, LVS, ERC, boundary checks).
• Analyze and resolve layout and verification issues.

Skills

Memory Layout

Custom Layout Design

Memory Leafcell Layout Libraries

Top-level Integration

Memory Architectures

Layout Optimization

FinFET Technology

Process Nodes

FinFET Rules & Constraints

Physical Verification Flow

DRC

LVS

ERC

Boundary Checks

Job description

We are looking for an experienced Memory Layout Engineer with strong expertise in custom layout design, memory leafcell layout, FinFET technology, and physical verification. The ideal candidate should have hands-on experience in designing optimized memory layouts and integrating memory leafcell libraries at the top level.

Key Responsibilities & Requirements:

• Hands-on experience in Memory Layout / Custom Layout Design.
• Experience in designing Memory Leafcell Layout Libraries from scratch, including top-level integration.
• Good understanding of different Memory Architectures and Memory Layout Structures.
• Strong knowledge of optimized layout design techniques for improved performance and area efficiency.
• Sound knowledge and hands-on experience in FinFET technology and advanced process nodes.
• Strong understanding of FinFET layout design rules, limitations, and process-related constraints.
• Proficiency in Physical Verification flow and debugging, including:
  • DRC (Design Rule Check)
  • LVS (Layout Versus Schematic)
  • ERC (Electrical Rule Check)
  • Boundary Condition checks
• Ability to analyze and resolve complex layout and physical verification issues.