Memory Design Engineer

Exiger Technologies; Kolkata District; On-site; INR 1,400,000 - 2,200,000; Full time

Job summary

Qualifications

• Strong experience in Memory Circuit Design.
• Hands-on transistor-level CMOS design.
• Proficient in SPICE tools (SPICE, Spectre, or HSPICE).
• Experience with PVT, Monte Carlo, and variability analysis.
• Knowledge of memory timing, power, leakage, and read/write margin analysis.
• Proficiency in Cadence Virtuoso.
• Understanding of DRC/LVS and physical design considerations.

Responsibilities

• Design and develop memory circuits such as SRAM, MRAM, RRAM, OTP/eFuse and related blocks.
• Perform transistor-level CMOS circuit design and optimization.
• Analyze memory timing paths and optimize read/write margins.
• Conduct SPICE/Spectre/HSPICE simulations across PVT corners.
• Perform Monte Carlo and variability analysis.
• Characterize memory for timing, power, leakage, and performance.
• Support Liberty (.lib) generation and characterization activities.
• Analyze parasitic impact and review layouts in collaboration with the Layout team.
• Perform functional and performance verification of memory circuits.
• Support silicon correlation and prepare characterization reports.
• Automate design and analysis flows using TCL and Shell scripting.
• Participate in design reviews and take ownership of assigned tasks.

Skills

Memory Circuit Design

transistor-level CMOS design

SPICE/Spectre/HSPICE

PVT Monte Carlo variability analysis

Memory timing/power/leakage analysis

Cadence Virtuoso

DRC/LVS and physical design

Shell scripting/TCL

cross-functional collaboration

Analytical problem solving

Liberty generation (.lib)

Tools

Liberty generation (.lib)

Job description

We are looking for an experienced Memory Design Engineer with strong expertise in custom memory circuit design, transistor-level CMOS design, simulation, and memory characterization. The ideal candidate should have hands‑on experience in designing and analyzing memory circuits and working closely with Layout and Verification teams.

Key Responsibilities

• Design and develop memory circuits such as SRAM, MRAM, RRAM, OTP/eFuse and related blocks.
• Perform transistor‑level CMOS circuit design and optimization.
• Analyze memory timing paths and optimize read/write margins.
• Conduct SPICE/Spectre/HSPICE simulations across PVT corners.
• Perform Monte Carlo and variability analysis.
• Characterize memory for timing, power, leakage, and performance.
• Support Liberty (.lib) generation and characterization activities.
• Analyze parasitic impact and review layouts in collaboration with the Layout team.
• Perform functional and performance verification of memory circuits.
• Support silicon correlation and prepare characterization reports.
• Automate design and analysis flows using TCL and Shell scripting.
• Participate in design reviews and take ownership of assigned tasks.

Required Skills

• Strong experience in Memory Circuit Design.
• Hands‑on experience with transistor‑level CMOS design.
• Good understanding of SRAM / MRAM / RRAM / OTP / eFuse concepts.
• Strong knowledge of SPICE, Spectre, or HSPICE.
• Experience with PVT, Monte Carlo, and variability analysis.
• Knowledge of memory timing, power, leakage, and read/write margin analysis.
• Proficiency in Cadence Virtuoso.
• Understanding of DRC/ LVS and physical design considerations.
• Scripting experience in TCL and Shell.
• Good analytical and problem‑solving skills.
• Strong communication and cross‑functional collaboration skills.

Preferred

• Experience with memory characterization and Liberty (.lib) generation.
• Exposure to silicon correlation and post‑silicon analysis.
• Experience working closely with Layout, Verification, and Physical Design teams.