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Mirafra Technologies in Bengaluru is seeking a Memory Layout Design Engineer with 2–10 years of experience to execute layout design for SRAM, CAM, and RF memories in 3nm and below process nodes. You will contribute to key memory building blocks, floor planning, and ensure EM/IR compliance.
The role requires proficiency in Cadence Virtuoso and Mentor Caliber, strong problem solving, and effective communication within a distributed team.
Job Role: Memory Layout Design Engineer (2 - 10 years exp.)
Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required.
Behavioral Traits: Ability to follow established procedures and work in a distributed team environment. Work independently to deliver high quality results on time.