Memory Layout Engineer

Prodapt ASIC services (Formerly Innovative Logic); Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

A leading technology firm in Bengaluru is seeking a mid-senior level professional for full-time custom layout design in semiconductor manufacturing. The role involves designing memory blocks like SRAM and DRAM, performing DRC/LVS checks, and collaborating with circuit design teams to meet performance and reliability targets. Previous experience with Cadence Virtuoso and deep submicron technologies is preferred. Be a part of a recognized company that values innovation and technological expertise.

Qualifications

• Mid-Senior level experience in custom layout design.
• Experience with TSMC technologies (2nm to 7nm) is preferred.

Responsibilities

• Responsible for custom layout design of memory blocks.
• Collaborate closely with circuit design teams.

Skills

Custom layout design of memory blocks

DRC/LVS checks

Layout optimization

Collaboration with circuit design teams

Hands-on experience in Cadence Virtuoso

Experience with Calibre/Assura

Knowledge of deep submicron technologies

Job description

Prodapt is the largest specialized player in the Connectedness industry. As an AI‑first strategic technology partner, Prodapt provides consulting, business reengineering, and managed services for the largest telecom and tech enterprises building networks and digital experiences of tomorrow. Prodapt has been recognized by Gartner as a Large, Telecom‑Native, Regional IT Service Provider. A “Great Place To Work® Certified™” company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of the 130‑year‑old business conglomerate The Jhaver Group, which employs over 32,000 people across 80+ locations globally.

Job Description

• Responsible for custom layout design of memory blocks (SRAM, DRAM, ROM, Register Files, etc.)
• Perform DRC/LVS checks, parasitic extraction, and layout optimization
• Collaborate closely with circuit design teams to ensure performance, area, and reliability targets are met
• Hands‑on experience in Cadence Virtuoso, Calibre/Assura, and deep submicron/FinFET technologies preferred (2nm to 7nm TSMC)

Seniority Level

Mid‑Senior level

Employment Type

Full‑time

Job Function

Consulting

Industries

Semiconductor Manufacturing