Job Opportunity For Memory Layout Engineer

Tech Mahindra; Bengaluru; On-site; INR 1,800,000 - 2,600,000; Full time

Job summary

Tech Mahindra in Bengaluru invites a Memory Layout Engineer to lead hands-on layout of memory blocks, including control logic, sense amplifiers and bit cell arrays. You will drive DRC/LVS checks, density verification and integration with memory IPs, collaborating with circuit designers and PDK teams to deliver optimized, manufacturable solutions.

The role requires deep knowledge of SRAM/DRAM architectures, sub-micron design challenges and proficiency with Cadence/Synopsys/ Mentor tools.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering.
• Hands-on memory layout experience in control logic, sense amps, I/O blocks, and bit cell arrays.
• Experience with SRAM/DRAM and memory IPs.
• Familiarity with DRC/LVS and physical closure.

Responsibilities

• Hands-on memory block layout including control logic, sense amps, and bit cell arrays.
• Experience with SRAM/DRAM, memory compiler IPs, and periphery circuits.
• Lead memory integration with DRC, LVS, and density verification.
• Collaborate with circuit design, verification, PDK and methodology teams.

Skills

Memory layout

SRAM/DRAM design

Memory periphery circuits

Physical verification (DRC/LVS)

Layout optimization (area/power/speed)

Cadence tools

Synopsys tools

IR/EM challenges

DFM guidelines

Collaboration with teams

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

Cadence tools

Synopsys tools

Mentor Graphics

Physical verification tools

Job description

Memory Layout Engineer

Experience: 48 years

Technology Nodes: TSMC/Samsung – 2nm, 3nm, 5nm, 7nm, and GF nodes

Qualifications: Bachelor's or Master's degree in Electrical Engineering,

Location - Bangalore

Key Skills & Responsibilities:

• Hands-on experience in layout of memory blocks like control logic, sense amplifiers, I/O blocks, bit cell array, decoders, etc.
• Strong experience in SRAM/DRAM, memory compiler IPs, and memory periphery circuits
• Expertise in top-level memory integration, DRC, LVS, density verification, and physical closure
• Understanding of IR/EM challenges in memory layouts
• Proficiency with Cadence/Synopsys tools for layout and Mentor/Cadence/Synopsys tools for physical verification
• Exposure to ultra-deep sub-micron design challenges and DFM guidelines
• Knowledge of memory architecture, bitcell layout concepts, and FinFET design rules
• Ability to optimize layout for area, power, speed, yield, and manufacturability
• Collaboration with circuit design, verification, PDK, and methodology teams