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We’re hiring an RTL Design Engineer who can own complex SoC or large subsystem blocks end-to-end. You’ll define micro‑architecture from specs, develop clean SystemVerilog/Verilog RTL, and drive integration, timing, power, and area closure with PD teams. Expect deep involvement through design reviews, bug closure, and silicon bring‑up.
You should bring 8+ years of hands‑on ASIC RTL experience with multiple production tapeouts, strong micro‑architecture skills, AMBA protocols, low‑power design, and clock/reset expertise. Solid exposure to DFT, synthesis constraints, ECO flows, and cross‑team collaboration is essential.
Bonus: experience with coherency, memory subsystems, DDR/PCIe, security blocks, SVA, or performance/power analysis. FPGA‑only, lint/CDC‑only, or management‑only backgrounds won’t meet the bar.
If you want real ownership and real silicon impact, this role is worth your time.
Best,
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