SeniorPrincipal ASIC RTL Design Engineer (SoC/Subsystem)

Proxelera; Dadri; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

A semiconductor manufacturing firm in India is seeking a mid-senior level RTL Design Engineer. The role involves defining micro-architecture from specifications, developing SystemVerilog/Verilog RTL, and collaborating on integration and closure tasks. Candidates should have over 8 years of experience in ASIC RTL design and strong architecture skills. This is a full-time position offering opportunities in a dynamic engineering environment.

Qualifications

• 8+ years of hands-on ASIC RTL experience with multiple production tape-outs.
• Strong architecture or micro-architecture skills.
• Deep understanding of low-power design and clock/reset expertise.

Responsibilities

• Define micro-architecture from specifications.
• Develop clean SystemVerilog/Verilog RTL.
• Drive integration, timing, power, and area closure.

Skills

ASIC RTL experience

Architecture skills

Micro-architecture skills

AMBA protocols

Low-power design

DFT exposure

Cross-team collaboration

Job description

Proxelera is India’s premium chip and system software product engineering partner. Our engineers take extreme passion in their assignments and deliver through their years of high‑quality experience to make your product successful. We understand the challenges of all aspects of product engineering – right from design planning stage to post‑silicon work. We also offer unparalleled quality of service in productization of your chip through reference system design and system software.

About the Job

We’re hiring an RTL Design Engineer who can own complex SoC or large subsystem blocks end‑to‑end. You’ll define micro‑architecture from specs, develop clean SystemVerilog/Verilog RTL, and drive integration, timing, power, and area closure with PD teams. Expect deep involvement through design reviews, bug closure, and silicon bring‑up.

Minimum Qualifications

• 8+ years of hands‑on ASIC RTL experience with multiple production tape‑outs.
• Strong architecture or micro‑architecture skills, AMBA protocols, low‑power design, and clock/reset expertise.
• Solid exposure to DFT, synthesis constraints, ECO flows, and cross‑team collaboration.

Seniority Level

Mid‑Senior level

Employment Type

Full‑time

Job Function

Design

Industry

Semiconductor Manufacturing

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