RTL Design Engineer

Proxelera PVT LTD; Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Benefits offered by this job

Health insurance

Paid time off

Professional development support

Job summary

Proxelera PVT LTD in Bengaluru is seeking an RTL Design Engineer to translate architecture into efficient RTL for AI, DSP, and networking silicon, with opportunities to work on SoC components and IP.

You will write synthesisable Verilog and SystemVerilog, collaborate with verification, architecture and physical design, and participate in design reviews, with room to expand into FPGA work and custom IP.

Qualifications

• Three or more years writing synthesisable Verilog or SystemVerilog with strong digital design fundamentals.
• Ability to translate architecture into efficient RTL and understand PPA trade-offs.
• Strong debugging and lint, CDC, and synthesis checks on your own code.

Responsibilities

• Write synthesisable Verilog and SystemVerilog for digital IP and SoC components.
• Collaborate with verification, architecture and physical design to maintain RTL quality.
• Perform PPA optimization, RTL simulation and unit-level validation.
• Participate in design and code reviews and contribute to team processes.
• Over time, contribute to FPGA design and custom IP development.

Skills

RTL Design

Verilog

SystemVerilog

Digital Design

PPA

Debugging

Tools

AXI

AHB

Memory Controllers

Job description

HERE'S HOW IT WORKS

Rather than your resume sitting in a queue, you have a conversation with Navii about your experience and what you want next. What you say reaches Proxelera's hiring team in your own words. It is a required step, and there is nothing to schedule.

NEXT STEP

A conversation with Navii about this role:

https://app.heynavii.ai/careers/rtl-design-engineer-431dd22d

ABOUT PROXELERA

Proxelera does end-to-end chip design from India, specification through silicon. Most chip companies use their India centres for validation or one slice of the process. Proxelera was built on the opposite idea: the whole system, owned ground up, in country. Over 190 engineers across the Bengaluru and Mysuru design centres, working on AI, DSP, AMS and wireless networking silicon.

THE ROLE

We are looking for an RTL Design Engineer to translate architecture into efficient RTL on AI, DSP and networking silicon.

Also a fit if you call yourself: RTL Engineer, Digital Design Engineer, ASIC Designer.

THE WORK

• Write synthesisable Verilog and SystemVerilog for digital IP and SoC components, turning specifications into micro-architecture.
• Work closely with verification, architecture and physical design to keep RTL quality high through lint, CDC and synthesis checks.
• Take on PPA optimisation, RTL simulation and unit-level validation, driving the quality of your own designs.
• Take part in design and code reviews, contributing to how the team works.
• Over time, work on FPGA design and custom IP development.

WHAT YOU'LL NEED

• Three or more years writing synthesisable Verilog or SystemVerilog, with a strong grounding in digital design fundamentals such as FSMs, pipelining and control design.
• The ability to translate architecture into efficient RTL and to understand PPA trade-offs.
• Strong debugging, and the habit of running lint, CDC and synthesis checks on your own code.

EVEN BETTER IF

• You have worked in SoC and IP design contexts, including AXI, AHB and memory controllers.
• You are familiar with low-power design techniques and DFT considerations.
• You script in Python or Perl, and you understand FPGA prototyping and board bring-up.

WHO THRIVES HERE

• You enjoy collaborative problem-solving and can navigate cross-functional teams.
• You want ownership, and you like driving projects from concept to execution.
• You are comfortable in a fast-paced setting and motivated by the chance to innovate in chip design.

THE TEAM

You will be part of a team focused on end-to-end chip design, reporting to Raghavendra Mohan V, who leads delivery and operations. The team works in a collaborative atmosphere with open communication and shared goals.

COMPENSATION AND LOGISTICS

Full-time, on-site five days a week, Bengaluru. The hiring team will share compensation details directly. Benefits include health insurance, paid time off and professional development support.