SOC RTL Design Engineer

Lattice Semiconductor; Maharashtra; On-site; INR 3,500,000 - 6,000,000; Full time

Benefits offered by this job

Job summary

Lattice Semiconductor in Pune, India, is seeking a SoC RTL Design Engineer to contribute to RTL design and full-chip integration within the HW design team. The role focuses on FPGA projects, RTL coding in Verilog/SystemVerilog, and ensuring quality checks throughout the design cycle.

Ideal candidates have 6+ years in logic design, experience with ARM/AXI/AMBA and PCIe, and the ability to collaborate across global teams while mentoring others.

Qualifications

• Requires 6+ years driving logic design across silicon projects.
• Experience with SoC integration, micro-architecture definition, and third‑party IP selection.
• Proficient with ARM processor, AXI/AMBA, ENET, PCIe, safety and security protocols; FPGA use is a plus.

Responsibilities

• Contribute as a key FPGA/SoC design contributor and drive key blocks and full-chip designs.
• Ensure design quality via lint, CDC, RDC, SDC checks and robust verification.
• Collaborate with architecture/micro-architect teams across sites and time zones.
• Mentor teammates, share best practices, and learn from others.

Skills

RTL design

SoC integration

ARM processor

AXI/AMBA bus

PCIe

FPGA designs

Debug architecture

Cross-site collaboration

Education

BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science or equivalent

Tools

Verilog/SystemVerilog

3rd-party IP selection

Job description

Lattice Overview

There is energy here… energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world‑class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Job Description

Lattice Semiconductor is seeking a SoC RTL Design Engineer to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow.

Role Specifics

• This is a full‑time individual contributor position located in Pune, India.
• The role will focus on FPGA projects concentrated in Pune and similar time zones.
• The qualified candidate will be working in RTL design, using best‑in‑class coding styles, algorithms, and both Verilog and System Verilog.
• The qualified candidate will be working in SoC integration and associated quality checks including lint, CDC, RDC, SDC etc.
• The role requires working with architect and micro‑architect team to understand and define design specifications.
• The successful candidate will be open and willing to both (a) teach best‑known methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and an open‑minded student.

Accountabilities

• Serve as a key contributor to FPGA design efforts.
• Drive logic design of key FPGA blocks & full chip and bring best‑in‑class methodologies to accelerate design time and improve design quality.
• Ensure design quality through assertions, checkers, and scripting.
• Develop strong relationships with worldwide teams.
• Mentor and develop strong partners and colleagues.
• Occasional travel as needed.

Required Skills

• BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science or equivalent.
• 6+ years of experience in driving logic design across a multitude of silicon projects.
• Expertise in SoC integration, defining micro‑architecture and experience of selecting 3rd‑party IP.
• Experience working with ARM processor, AXI, AMBA bus, ENET, PCIe, safety and security protocols, debug architecture will be a plus.
• Familiarity with FPGA designs, use‑cases, and design considerations is a plus.
• Independent worker and leader with demonstrated problem‑solving abilities.
• Proven ability to work with multiple groups across different sites and time zones.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in India.

EEO Statement

Applications are welcome from all qualified candidates.