Sr. Memory Layout Design Engineer

Broadcom Inc.; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Broadcom Inc. seeks an experienced layout engineer focused on memory design in Bengaluru. You will apply layout guidelines, manage schedules, and drive end-to-end deliverables for submicron CMOS processes. Collaboration with SOC/library teams and ongoing scripting/automation are part of the role.

The ideal candidate has 8+ years in memory layout, strong verification skills (DRC/LVS), and proficiency with Cadence and CALIBRE tools, plus leadership capabilities.

Qualifications

• Bachelor's degree required in a relevant engineering field.
• 8+ years of experience with memory/layout design and verification.
• Strong memory layout knowledge for submicron nodes (7nm/5nm/3nm/2nm).
• Proficient with Cadence tools and memory layouts for CMOS processes.
• Experience leading junior engineers and coordinating projects.

Responsibilities

• Translate layout guidelines and process rules into high quality layouts.
• Plan schedules, timelines, and layout floor-planning end-to-end.
• Deliver start-to-end work with on-time quality within scope.
• Adapt to new methodologies and collaborate with SOC/library teams.
• Contribute to layout scripting and automation initiatives.

Skills

Memory layout

Physical verification

Digital layout

Analog layout

Team leadership

Submicron processes

Memory architecture

Script programming

AI/automation in layout

Education

Bachelor's degree

Tools

VIRTUOSO XL

VXL

EXL

CALIBRE

Hercules

Cadence Schematic Capture

Job description

Job Requirements

• Minimum 8 years of experience with strong layout knowledge
• Bachelor's degree required.
• Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).
• Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm).
• Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.

Job Description

• Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.
• Manage scheduling, timelines, and layout floor-planning.
• Responsible for start to end deliverables with quality within the planned schedule.
• Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.
• Able to think and help in layout scripting and automation

Skill Set (Memory)

• Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.
• Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.
• Proficiency in floor-planning, hierarchy layout, and chip integration.
• Understanding of memory architecture, RC requirement, ability to plan signal and power, based on the layout guidelines
• Knowledge of AI, automation in layout, Script Programming and SKILL Programming
• Ability to lead, train junior engineers, and manage projects effectively.
• Good knowledge of memory layout topology; experience with memory compilers is a plus.
• Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.
• Self-reliant with the ability to work both independently and collaboratively.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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