RTL Design Engineer

Capgemini Engineering; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

A leading engineering firm is hiring for Design Verification & Analog Layout & DFT positions in Bengaluru, India. The candidate should have over 7 years of experience with a strong focus on SOC integration and RTL coding. Key responsibilities include handling various SOC flows and scripting. Competitive salary and full-time employment offered.

Qualifications

• 7+ years of experience in relevant field.
• Good understanding of SoC flows.
• Knowledge of scripting language.

Responsibilities

• Integration of SOC & RTL coding.
• Experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP.
• Awareness of SoC flow like Spyglass-Lint/Synthesis (DC)/CDC.

Skills

VHDL

Verilog

Micro-architecture

RTL coding

CDC

Lint

Synthesis

STA

IP development

SoC integration

VCLP

scripting - Perl

scripting - Python

scripting - Shell

scripting - Tcl

Tools

Spyglass

Cadence

Job description

Capgemini Engineering is hiring for Design Verification & Analog Layout & DFT Positions.

Job Description

Experience: 7+ years

Key Responsibilities:

• Candidate should be good in Integration of SOC & RTL coding.
• Should be aware of SoC flow like Spyglass-Lint/Synthesis (DC)/CDC.
• Should be aware of scripting language.
• Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP.
• Should have good understanding of SoC flows.

Primary Skills

• VHDL, Verilog, Micro-architecture, RTL coding, CDC, Lint, Synthesis, STA, IP development, SoC integration, VCLP, scripting - Perl, Python, Shell, and Tcl.

Secondary Skills

• Synopsis/Cadence tool flow, ARM Coretex, DMA, DDR, SPI, I2C, UART, AHB/AXI/APB, Ethernet, USB, PCIe, Mipi CSI/DSI, LPDDR.

Seniority level

Mid-Senior level

Employment type

Full-time

Capgemini Engineering is an equal opportunities employer and welcomes applications from all qualified candidates.