Senior RTL Design Engineer - CPU And Microarchitecture

Weekday AI (YC W21); Bengaluru; On-site; INR 1,200,000 - 2,500,000; Full time

Job summary

Weekday AI (YC W21) in Bengaluru, India seeks a Senior RTL Design Engineer – CPU & Microarchitecture to design high-performance ASIC/SoC architectures focusing on CPU cores and processor subsystems.

You will translate microarchitecture specs into RTL, develop pipelines, caches, MMU, and interconnects, and collaborate across architecture, verification, physical design, and validation teams.

Qualifications

• 5+ years of ASIC/SoC RTL design experience.
• 2+ years of CPU core RTL design experience.
• Strong SystemVerilog, Verilog, and VHDL skills.
• Experience with AMBA protocols (AXI, AHB, APB, CHI).

Responsibilities

• Design, develop, and maintain synthesizable RTL for CPU cores and processor subsystems.
• Translate CPU microarchitecture specifications into RTL implementations.
• Develop and optimise instruction execution pipelines, hazard handling, branch prediction.
• Design and integrate L1/L2 cache, MMU, interrupts, and memory subsystem components.
• Develop scripts and automation using Python, Perl, TCL, Bash, or similar languages.
• Collaborate with verification engineers to support functional verification and debugging.

Skills

SystemVerilog

Verilog

VHDL

CPU microarchitecture

Python

Perl

TCL

Bash

AXI protocol

AMBA protocols

Education

B.Tech/M.Tech in Electronics, VLSI, Microelectronics, Computer Engineering, or a related discipline

Tools

Synopsys SpyGlass

VCS

Design Compiler

Cadence Genus

Xcelium

Job description

Job Description

This role is for one of the Weekday clients

Salary range: Rs 1200000 - Rs 2500000 (ie INR 12-25 LPA)

Experience: 5+ yrs

Location: Bengaluru, Hyderabad, Telangana, India

Job Type: Full-time

We are looking for an experienced Senior RTL Design Engineer – CPU & Microarchitecture to contribute to the design and development of high-performance ASIC and SoC architectures, with a strong focus on CPU cores and processor subsystems.

The ideal candidate will have deep expertise in RTL design, SystemVerilog, CPU microarchitecture, and computer organization, along with practical experience developing complex digital designs for production silicon. You will contribute to architecture implementation, RTL development, verification collaboration, synthesis readiness, and technical debugging across the SoC development lifecycle.

KEY RESPONSIBILITIES

• Design, develop, and maintain synthesizableRTL for CPU cores and processor subsystems.
• Translate CPU microarchitecture specifications into efficient and scalable RTL implementations.
• Develop and optimise instruction execution pipelines, hazard handling, branch prediction, and related CPU datapath/control logic.
• Design and integrateL1/L2 cache, MMU, interrupt, and memory subsystemcomponents.
• Implement and integrate AMBA-based interfaces and interconnect protocols includingAXI, AHB, APB, ACE, and CHI.
• Develop high-quality RTL usingSystemVerilog, Verilog, and VHDL.
• Participate in microarchitecture reviews, RTL design reviews, and technical design discussions.
• Perform RTL linting, structural analysis, and front-end quality checks using tools such asSynopsys SpyGlass and VCS.
• Support synthesis and design implementation activities usingSynopsys Design Compiler or Cadence Genus.
• Collaborate with verification engineers to support functional verification, debug, and design quality.
• Analyse simulation results, identify RTL issues, and drive root-cause resolution.
• Develop scripts and automation usingPython, Perl, TCL, Bash, or similar scripting languages.
• Support FPGA prototyping and hardware validation activities where required.
• Contribute to post-silicon bring-up, debugging, and issue resolution.
• Support performance, power, area, and timing optimisation of CPU and SoC designs.
• Apply appropriatelow-power design techniqueswhere required.
• Maintain technical documentation related to RTL, microarchitecture, interfaces, and design decisions.
• Collaborate with architecture, verification, physical design, validation, and system teams throughout the development lifecycle.
• Mentor junior engineers and contribute to RTL design standards and best practices.

WHAT MAKES YOU A GREAT FIT

• 5+ years of experiencein ASIC/SoC RTL design, including at least2+ years of dedicated experience in CPU core or processor subsystem RTL design.
• Strong hands-on expertise inSystemVerilog, Verilog, and VHDL.
• Strong understanding ofCPU microarchitecture and computer organization.
• Practical knowledge of instruction pipelines, hazard handling, branch prediction,L1/L2 caches, MMU, interrupts, and processor subsystems.
• Strong experience withAMBA protocols, particularly AXI, AHB, APB, ACE, and CHI.
• Hands-on experience with front-end EDA tools such asSynopsys SpyGlass, VCS, Design Compiler, Cadence Genus, or Xcelium.
• Strong scripting and automation skills usingPython, Perl, TCL, Bash, or equivalent.
• Experience with at least one processor architecture such asRISC-V, ARM, x86, or proprietary CPU architecturesis preferred.
• Understanding of RTL synthesis, timing considerations, design quality, and ASIC/SoC development flows.
• Exposure tolow-power design methodologiesis an advantage.
• Experience withFPGA prototyping, post-silicon bring-up, and hardware debuggingis desirable.
• Knowledge of assembly programming and processor instruction sets is an advantage.
• Strong debugging, analytical, and problem-solving skills.
• Ability to work effectively with architecture, verification, physical design, and validation teams.
• Strong understanding of digital design principles and RTL coding best practices.
• Excellent communication and technical documentation skills.
• Ability to take ownership of complex design problems and deliver high-quality solutions within project timelines.
• B.Tech/M.Tech in Electronics, VLSI, Microelectronics, Computer Engineering, or a related disciplineis preferred.