Senior RTL Engineer

SignatureIP Corporation; India; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

SignatureIP Corporation in India seeks an accomplished SoC architect with 8+ years of experience to lead RTL design and micro‑architecture for high‑speed interfaces and NoC architectures. You will collaborate across hardware and software teams to define and optimize performance targets while evaluating third‑party IP.

Expertise in SystemVerilog and UVM is essential to model architecture and verify critical paths, with a strong emphasis on power, area, and cross‑functional collaboration.

Qualifications

• Bachelor's or higher in Electrical/Computer Engineering or CS; advanced degrees preferred.
• 8+ years in SoC and RTL architecture roles with strong RTL design experience.
• Proven experience with high-speed interfaces (PCIe Gen 4/5/6) and NoC.
• Deep knowledge of memory subsystems and cache coherency protocols.
• Proficiency in SystemVerilog and UVM for architecture modeling.
• Ability to define, evaluate, and optimize system-level performance and power.
• Experience with third-party IP integration and design trade-offs.
• Strong communication and cross-functional collaboration skills.

Responsibilities

• Define and drive RTL design and micro-architecture strategies for complex SoCs.
• Lead NoC architecture work and optimize memory subsystem performance.
• Evaluate and integrate third-party IP while balancing power, area, and speed.
• Model architecture using SystemVerilog and UVM; verify critical paths.
• Collaborate with cross-functional teams across hardware and software.
• Define system-level performance targets and monitor power efficiency.

Skills

RTL design

SoC architecture

High-speed interfaces

NoC design

Cache coherency

SystemVerilog

UVM

Cross-functional collaboration

Power optimization

Education

BE

BTech

MTech

MS

PhD

Electronics

Electrical

Computer Engineering or Computer Science Engineering

Tools

SystemVerilog

UVM

PCIe

CXL

Job description

Education

• BE
• BTech
• MTech
• MS
• PhD
• Electronics
• Electrical
• Computer Engineering or Computer Science Engineering

Job Description

• Strong RTL design and micro-architecture skills.
• Expertise in SoC architecture and high-speed interfaces (PCIe Gen 4/5/6, CXL 2.0/3.0).
• Deep knowledge of Network-on-Chip (NoC) design and memory subsystem architecture.
• Hands‑on experience with cache coherency protocols and interface protocols.
• Proficiency in SystemVerilog and UVM for architecture modeling.
• Ability to define, evaluate, and optimize system‑level performance and power.
• Familiarity with third‑party IP integration and design trade‑offs.
• Strong communication and cross‑functional collaboration skills.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science (Master’s or PhD preferred).
• Minimum 8+ years of industry experience in SoC and RTL architecture roles.