RTL Design - Microarchitecture

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 3,000,000 - 4,200,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd in Bengaluru is seeking an experienced ASIC Design Engineer to lead microarchitecture definition, RTL design, and implementation of high-speed interface IPs. You will collaborate with cross-functional teams to deliver silicon solutions that balance performance, power, and area.

The role emphasizes design for PCIe Gen4/5, 100G/400G Ethernet, USB3/4, and SerDes-based interfaces, with RTL in Verilog/SystemVerilog, and close coordination with verification and physical

Qualifications

• 10+ years of experience in ASIC design.
• Experience with PCIe Gen4/Gen5, 100G/400G Ethernet, USB3/USB4 SerDes.

Responsibilities

• Architect and design high-performance ASIC SoCs, targeting high-speed protocols PCIe Gen4/Gen5, 100G/400G Ethernet, USB3/4, SerDes-based interfaces.
• Develop RTL using Verilog/SystemVerilog with a focus on performance, power, and area (PPA) optimization
• Define and document micro-architecture and interface specifications for protocol IPs
• Collaborate with verification teams to develop test plans, debug failures, and achieve coverage closure
• Work closely with physical design teams on synthesis, timing closure, and floor planning support
• Analyze and debug silicon bring-up issues
• Integrate third-party IPs (SerDes, PHYs) and ensure proper functionality and interoperability
• Participate in design reviews and ensure adherence to design methodologies and best practices
• Drive design quality through lint, CDC, and verification readiness checks

Job description

As an ASIC Design Engineer, you will play a key role in microarchitecture definition, RTL design, and implementation of high-speed interface IPs. You will collaborate with cross-functional teams to deliver high-performance, power-efficient, and scalable silicon solutions.

Key Responsibilities:

• Experience 10+yrs , Bangalore location
• Architect and design high-performance ASIC SoCs, targeting high-speed protocols PCIe Gen4/5, 100G/400G Ethernet, USB3/4, SerDes-based interfaces.
• Develop RTL using Verilog/System Verilog with a focus on performance, power, and area (PPA) optimization
• Define and document micro-architecture and interface specifications for protocol IPs
• Collaborate with verification teams to develop test plans, debug failures, and achieve coverage closure
• Work closely with physical design teams on synthesis, timing closure, and floor planning support
• Analyze and debug silicon bring-up issues related to high-speed interfaces
• Integrate third-party IPs (SerDes, PHYs) and ensure proper functionality and interoperability
• Participate in design reviews and ensure adherence to design methodologies and best practices
• Drive design quality through lint, CDC, and verification readiness checks

Required Skills:

• Deep understanding of high-speed protocols, such as: PCIe (Gen4/Gen5), Ethernet (100G/400G), USB (USB3/USB4), SerDes-based architectures.
• Solid background in microarchitecture design and trade-off analysis
• Experience in SoC integration and subsystem design
• Good knowledge of synthesis, STA, and physical design considerations

Good to Have:

• Experience in silicon bring-up and post-silicon debug
• Exposure to advanced technology nodes and high-frequency designs

What We’re Looking For:

• Strong debugging and analytical skills
• Ability to work across cross-functional teams
• Ownership mindset and attention to detail
• Passion for building high-performance silicon