Senior RTL Engineer

Semiengineering; Khordha; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Semiengineering in Odisha, India seeks an experienced SoC architect with strong RTL design and micro-architecture skills to lead high-speed interfaces and NoC design.

You'll model with SystemVerilog and UVM, work on memory subsystem architecture, and ensure cache coherency and protocol compliance across PCIe Gen4/5/6 and CXL 2.0/3.0.

Qualifications

• Strong RTL design and micro-architecture skills.
• Expertise in SoC architecture and high-speed interfaces (PCIe Gen4/5/6, CXL 2.0/3.0).
• Deep knowledge of NoC design and memory subsystem architecture.
• Hands-on experience with cache coherency protocols and interface protocols.
• Proficiency in SystemVerilog and UVM for architecture modeling.

Skills

RTL design

micro-architecture

SoC architecture

PCIe interfaces

CXL interfaces

NoC design

memory subsystem

cache coherency

interface protocols

SystemVerilog

UVM

Tools

Job description

Job Description

• Strong RTL design and micro-architecture skills.
• Expertise in SoC architecture and high-speed interfaces (PCIe Gen 4/5/6, CXL 2.0/3.0).
• Deep knowledge of Network-on-Chip (NoC) design and memory subsystem architecture.
• Hands-on experience with cache coherency protocols and interface protocols.
• Proficiency in SystemVerilog and UVM for architecture modeling.