CPU RTL Engineer

G.t.d Technologies; Hyderabad, Bengaluru; Hybride; INR 1 800 000 - 3 200 000; Plein temps

Résumé du poste

G.t.d Technologies in Hyderabad, India, is seeking an experienced ASIC/SoC RTL Design engineer with a strong focus on CPU cores. The role requires deep expertise in CPU subsystem RTL and hands-on work with SystemVerilog, Verilog and VHDL.

You will contribute to RTL development, verification readiness, and integration within SoC projects, with exposure to AMBA protocols and FPGA or silicon bring-up. A minimum 5+ years in ASIC/SoC RTL design is expected, including 2+ years in CPU core RTL.

Qualifications

• 5+ years in ASIC/SoC RTL design with 2+ years in CPU core RTL design.
• Proficient in SystemVerilog, Verilog and VHDL.
• Experience with AMBA protocols (AXI, AHB, APB, ACE, CHI).
• Hands-on with SpyGlass, VCS, Design Compiler or Genus/Xcelium.
• Scripting in Python, Perl, TCL or Bash.

Connaissances

ASIC RTL Design

SoC RTL Design

CPU Core RTL Design

SystemVerilog

Verilog

VHDL

RISC-V/ARM/x86 cores

AMBA AXI/AHB/APB

Python scripting

Formation

B.Tech / M.Tech in Electronics / VLSI / Microelectronics / Computer Engineering

Outils

SpyGlass

VCS

Design Compiler

Genus/Xcelium

Description du poste

Experience: 5+ Years (Minimum 2+ Years in CPU/Processor RTL Design)

Required Qualifications & Skills

• Education: B.Tech / M.Tech in Electronics, VLSI, Microelectronics, or Computer Engineering.
• Experience: 5+ total years in ASIC/SoC RTL Design, with at least 2+ years dedicated to CPU core or processor subsystem RTL design (RISC-V, ARM, x86, or proprietary cores).
• Hardware Description Languages: Proficient in SystemVerilog, Verilog, and VHDL.
• CPU Microarchitecture Knowledge: Understanding of computer organization instruction execution pipelines, hazard handling, branch prediction, L1/L2 caches, memory management units (MMU), and interrupts.
• Bus Protocols: Hands-on experience with AMBA protocols (AXI, AHB, APB, ACE, CHI).
• Front-End Tools: Hands-on experience with Synopsys SpyGlass (Lint/CDC), VCS, Design Compiler (DC), or Cadence Genus/Xcelium.
• Scripting: Python, Perl, TCL, or Bash for automation. Preferred Qualifications

Preferred Qualifications

• Experience with low-power design techniques (Clock Gating, UPF/CPF intent definition).
• Exposure to FPGA prototyping or post-silicon bring-up and debug.
• Familiarity with assembly programming (RISC-V/ARM) for basic diagnostic bring-up tests.