RTL Design Engineer

Weekday AI (YC W21); Bengaluru; On-site; INR 1,500,000 - 3,000,000; Full time

Job summary

Weekday AI is seeking an experienced RTL Design Engineer to work on complex SoC designs for a client in Bengaluru and Hyderabad. You will translate architectural specs into robust, synthesizable RTL using Verilog/SystemVerilog, focusing on low-power techniques and UPF-based power management.

The role requires 5–11 years in RTL/Digital Design, strong microarchitecture expertise, and collaboration with architecture, verification, DFT, and physical design teams to meet performance and power targets.

Qualifications

• 5–11 years of RTL/Digital Design experience.
• Strong Verilog/SystemVerilog RTL expertise.
• Deep understanding of microarchitecture.
• Proficiency with UPF and low-power design concepts.
• Knowledge of power domains, isolation cells, level shifters, retention strategies.
• Strong fundamentals in FSMs, datapaths, pipelining, clocking, resets.
• Experience on complex SoC/ASIC/CPU designs.
• Ability to analyze and resolve timing, power, and performance issues.
• Experience collaborating with architecture, verification, DFT, physical design, and STA.

Responsibilities

• Design, develop, and maintain RTL modules using Verilog/SystemVerilog based on specs.
• Translate specifications into synthesizable RTL.
• Develop datapaths, control logic, interfaces, state machines for SoC designs.
• Implement UPF-based low-power intent and power-domain management.
• Translate system-level specs into efficient RTL; consider PPAT factors.
• Collaborate with verification teams for verification strategies and debugging.
• Work with physical design teams on synthesis, timing, and power issues.
• Perform RTL quality checks, lint, CDC, and design reviews.

Skills

Verilog/SystemVerilog

RTL design

Microarchitecture

UPF

Low-power design

Power domains

FSMs/datapaths

Clocking/reset strategies

Synchronous design

SoC/ASIC/IP-level

Cross-functional collaboration

Education

Bachelor's or Master's in Electronics/EE/CE

Tools

EDA tools

Simulation environments

Python scripting

Job description

Job Description

This role is for one of Weekday's clients

Min Experience: 5+ years
Location: Hyderabad, Bengaluru
JobType: full-time

We are seeking an experienced RTL Design Engineer with 5-11 years of hands-on experience in digital design and semiconductor development. The ideal candidate will have strong expertise in RTL design, microarchitecture, and UPF (Unified Power Format), with a solid understanding of low-power design methodologies and SoC development.

You will be responsible for translating architectural and microarchitectural specifications into robust, synthesizable RTL, collaborating with architecture, verification, physical design, and power teams, and ensuring designs meet functional, performance, area, and power requirements.

Key Responsibilities

• Design, develop, and maintain high-quality RTL modules using Verilog/SystemVerilog based on architectural and microarchitectural specifications.
• Work closely with architects to understand requirements and contribute to defining and refining microarchitecture.
• Develop datapaths, control logic, interfaces, state machines, and other digital blocks for complex SoC designs.
• Implement and maintain UPF-based low-power intent, including power domains, isolation strategies, level shifters, retention, power states, and related power-management requirements.
• Translate system-level and block-level specifications into efficient, synthesizable RTL.
• Analyze design trade-offs involving performance, power, area, and timing (PPAT).
• Collaborate with verification engineers to develop verification strategies, resolve functional issues, and support simulation and debug activities.
• Work with physical design teams to address synthesis, timing, power, and implementation-related issues.
• Perform RTL quality checks, lint analysis, CDC-related reviews, and design reviews as required.
• Debug RTL and simulation issues and identify root causes across complex design environments.
• Participate in design reviews and contribute to coding standards, design methodologies, and process improvements.
• Ensure RTL complies with industry-standard design practices and project specifications.
• Support integration of IPs and subsystems into larger SoC environments.
• Review and improve existing RTL for performance, power efficiency, scalability, and maintainability.

Must-Have Skills

• 5-11 years of experience in RTL/Digital Design.
• Strong hands-on expertise in Verilog/SystemVerilog RTL design.
• Strong understanding of microarchitecture and experience converting architectural specifications into RTL implementations.
• Solid experience with UPF (Unified Power Format) and low-power design concepts.
• Good understanding of power domains, isolation cells, level shifters, retention strategies, and power-state management.
• Strong knowledge of digital design fundamentals, including FSMs, datapaths, pipelining, clocking, reset strategies, and synchronous design.
• Experience working on complex SoC, ASIC, CPU, subsystem, or IP-level designs.
• Ability to analyze and resolve functional, performance, power and timing-related design issues.
• Experience collaborating with cross-functional teams including architecture, verification, DFT, physical design, and STA.

Good-to-Have Skills

• Experience with low-power SoC design and power-management architectures.
• Familiarity with synthesis, STA, lint, CDC, and RTL quality tools.
• Exposure to semiconductor design flows and ASIC development methodologies.
• Knowledge of clock-domain and reset-domain crossing methodologies.
• Experience with scripting languages such as Python, Perl, or Tcl.
• Familiarity with industry-standard EDA tools and simulation environments.
• Experience with block-level as well as top-level SoC integration.

Qualifications

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field, with strong experience in digital/RTL design.