Rtl Design Engineer 2307

Sunrise Biztech Systems; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. in Hyderabad is seeking an RTL Design Engineer 2 to develop synthesizable RTL using Verilog/SystemVerilog and to design IPs/subsystems with AXI/AXI4-Lite/APB protocols.

The role requires handling clock/reset architecture, address mapping, and configuration integration. You will drive lint, CDC, RDC, and synthesis signoff while debugging RTL quality issues and ensuring clean handoff to the implementation teams.

Qualifications

• Proficiency in Verilog and SystemVerilog for synthesizable RTL design.
• Experience with AXI, AXI4-Lite, AHB, and APB protocols.
• Strong understanding of clock/reset architecture, address mapping, and integration.
• Familiarity with linting, CDC, RDC, X-propagation, and synthesis signoff processes.
• Ability to debug RTL quality issues and ensure clean handoff to implementation teams.
• Experience with automation using Python/Perl/Tcl for quality checks and reporting.

Responsibilities

• Develop synthesizable RTL using Verilog/SystemVerilog.
• Design and integrate IPs/subsystems with AXI/AXI4-Lite/APB protocols.
• Manage clock/reset, address mapping and configuration integration.
• Conduct RTL reviews and ensure protocol compliance.
• Automate quality checks and regressions using Python/Perl/Tcl.
• Collaborate with architecture, verification, and implementation teams for production-ready RTL.

Skills

Verilog

SystemVerilog

RTL Design

AXI/AHB/APB

Lint

CDC

RDC

Synthesis

RTL Signoff

Subsystem Integration

Scripting/Automation

Education

BE/B.Tech/M.Tech in Electronics, Electrical, VLSI, or related field

Job description

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Job Title

RTL Design Engineer 2

Work Location

Hyderabad

Contract Duration

12 Months

Key Responsibilities

• Develop synthesizable RTL using Verilog/SystemVerilog.
• Design and integrate IPs/subsystems using AXI, AXI4-Lite, AHB, and APB protocols.
• Handle clock/reset architecture, address mapping, and configuration integration.
• Drive Lint, CDC, RDC, X-propagation, structural checks, and synthesis signoff.
• Debug and resolve RTL quality violations and ensure clean design handoff.
• Perform RTL reviews and ensure protocol/methodology compliance.
• Develop Python/Perl/Tcl automation for quality checks, regressions, and reporting.
• Collaborate with architecture, verification, and implementation teams to ensure production-ready RTL.

Must-Have Skills

Verilog, SystemVerilog, RTL Design, AXI/AHB/APB, Lint, CDC, RDC, Synthesis, RTL Signoff, Subsystem Integration, Scripting/Automation.

Education

BE/B.Tech/M.Tech in Electronics, Electrical, VLSI, or related field.