RTL Design Engineer 5

Sunrise Biztech Systems; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. is seeking an experienced RTL Design Engineer to own IP and top-level ASIC verification for complex SerDes subsystems in Bengaluru. The role requires 10+ years of experience with SystemVerilog/UVM and hands-on testbench development.

The position is a 12-month contract based in Bangalore, with collaboration across digital, analog and firmware teams to ensure system-level interface integrity.

Qualifications

• 10+ years of RTL design/verification experience required.
• Strong proficiency in SystemVerilog/UVM and ASIC verification.
• Experience with SerDes subsystems is a plus.

Responsibilities

• Spec Review: Analyze design specs and align test plans with designers.
• Testbench Development: Build/upgrade UVM testbenches and close coverage.
• Cross-Team Integration: Collaborate with RTL, analog and firmware teams to verify interfaces.
• Behavioral model verification: Validate analog model and firmware interactions in digital testbench.
• Productivity: Use automation/AI tools to speed up debugging.

Tools

Verilog

SystemVerilog

UVM

IP TB development

EDA tools Verdi

EDA tools VCS

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: RTL Design Engineer

Experience: 10+ Years

Location: BANGALORE

Contract tenure: 12 Months

Job Description

Scope: Owns IP and top-level ASIC verification for complex SerDes subsystems.

Domain: Verifies digital RTL integrated with analog behavioral models using SystemVerilog/UVM.

Alignment: Ensures seamless functionality across digital, analog, and firmware boundaries.

Metrics: Drives testbench architecture and test planning to achieve coverage closure.

Job Responsibilities / Day-to-Day Activities

• Spec Review: Analyze design specs and collaborate with designers to align test plans.
• Testbench Development: Build or upgrade UVM testbenches, write tests, and close coverage.
• Cross-Team Integration: Work with RTL, analog, and firmware teams to bridge design gaps and verify system-level interfaces.
• Behavioral Model Verification: Validate subsystem functionality including analog model and firmware interactions in the digital testbench.
• Productivity: Leverage approved automation and AI tools to accelerate debugging and triage.

Top 3 mandatory (primary) skills:

• Verilog, system verilog, UVM, IP level TB component development, Mastery in EDA tools (Verdi,vcs) etc

Good to have (secondary) skills:

• Comfortable in scripting for automation
• AI tools usage
• Experience in digital+analog verification
• Soft Skills
• Converse with teams across various geographies