Senior RTL Design Engineer

LeadSoc Technologies Pvt Ltd; Hyderabad; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd is seeking a Senior RTL Design Engineer to develop synthesizable RTL for complex SoC/IP designs and to ensure ultra-high quality through lint and CDC checks. The role involves hands-on Ethernet protocol expertise, microarchitecture translation to RTL, and collaboration with Architecture, DV, STA, and Physical Design teams.

You will drive RTL optimizations for PPA, timing, area and power.

Qualifications

• Develop and integrate synthesizable RTL for complex SoC/IP designs.
• Strong hands-on experience with Ethernet protocols/IP and high-speed networking designs.
• Translate microarchitecture specifications into efficient RTL.
• Perform Lint, CDC/RDC and RTL quality checks using SpyGlass.
• Debug and resolve RTL, CDC, lint and functional issues.
• Collaborate with Architecture, DV, STA and Physical Design teams.
• Drive RTL optimization for PPA, timing, area and power.

Responsibilities

• Develop and integrate synthesizable RTL for complex SoC/IP designs.
• Collaborate with Architecture, DV, STA and Physical Design teams to ensure design quality.
• Translate microarchitecture specifications into efficient RTL and validate through linting and checks.
• Debug and resolve RTL, CDC, lint and functional issues during integration and tape-out.
• Drive RTL optimization focusing on PPA, timing, area, and power targets.

Skills

RTL design

Ethernet IP design

Lint/CDC

SpyGlass

Microarchitecture

Synthesis & PPA

Tools

SpyGlass

Job description

We are looking for a Senior RTL Design Engineer with strong hands-on expertise in Ethernet-based SoC/IP design, RTL development, and design quality checks.

Key Responsibilities

• Develop and integrate synthesizable RTL for complex SoC/IP designs.
• Strong hands-on experience with Ethernet protocols/IP and high-speed networking designs.
• Translate microarchitecture specifications into efficient RTL.
• Perform Lint, CDC/RDC and RTL quality checks using SpyGlass.
• Debug and resolve RTL, CDC, lint and functional issues.
• Collaborate with Architecture, DV, STA and Physical Design teams.
• Drive RTL optimization for PPA, timing, area and power.

Core Technical Skills

• Solid microarchitecture understanding and ability to work from specifications.
• Strong Ethernet knowledge — MAC/PCS/PHY, 10G/25G/100G/400G exposure preferred.
• Hands-on experience with SpyGlass Lint & CDC.
• Strong understanding of CDC, reset architecture, clocking and RTL coding practices.
• Experience with synthesis, timing and PPA optimization.
• Strong debugging and problem-solving skills.

Ideal Candidate:

A hands-on RTL engineer with strong Ethernet + Microarchitecture + Lint/CDC + SpyGlass expertise and experience delivering production-quality SoC/IP designs.