SoC Lead / RTL Design Manager

BITSILICA; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

BITSILICA in Bengaluru, India, is seeking an experienced RTL Design Manager to lead ASIC/SoC development and drive high-impact projects. The role focuses on delivering robust RTL design flows and coordinating across teams.

The candidate will bring deep expertise in Ethernet protocols, PCIe and Ethernet subsystems, Verilog/SystemVerilog RTL design, and high-speed interfaces. Strong debugging, CDC/lint/synthesis/timing analysis, and bus protocol knowledge are essential.

Qualifications

• Strong expertise in Ethernet protocols and architecture.
• Expertise in PCIe and Ethernet subsystem integration.
• Experience with Verilog or SystemVerilog RTL design.
• Understanding of high-speed interfaces and networking protocols.
• Experience with CDC, lint, synthesis, and timing analysis.
• Familiarity with AXI/AHB/APB bus protocols.
• Strong debugging and problem-solving skills.

Skills

Ethernet protocols

PCIe/Ethernet Subsystem

Verilog/SystemVerilog RTL

High-speed interfaces

CDC/Lint/Synthesis/Timing

AXI/AHB/APB buses

Debugging skills

Job description

We are looking for an RTL Design Manager to lead high-impact ASIC/SoC development.

Minimum Qualifications:

• Strong expertise in Ethernet protocols and architecture.
• Expertise on PCIE /Ethernet Subsystem Integration.
• Experience with Verilog / SystemVerilog RTL design.
• Understanding of high-speed interfaces and networking protocols.
• Experience with CDC, lint, synthesis, and timing analysis.
• Familiarity with AXI / AHB / APB bus protocols.
• Strong debugging and problem-solving skills.