Rtl Design Engineer

Allegis Group; Hyderabad; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Allegis Group is seeking a Design Engineer with 4-6 years of RTL design experience for a product-based environment focused on RTL design, subsystem integration and silicon-quality ownership.

You will develop synthesizable RTL, drive IP/subsystem integration, and ensure signoff readiness across lint, CDC, RDC issues, with emphasis on automation to improve RTL development processes.

Qualifications

• 4–6 years of RTL design experience and silicon-quality signoff.
• Experience in IP/Subsystem/SoC integration.

Responsibilities

• Develop high-quality synthesizable RTL.
• Drive IP and subsystem integration.
• Own RTL quality from development to handoff.
• Drive closure of Lint, CDC, RDC, X-propagation, and synthesis issues.
• Ensure clean signoff and production-ready RTL.
• Improve RTL development methodologies through automation.

Skills

Verilog

SystemVerilog

IP/Subsystem/SoC Integration

AMBA AXI Protocols

Lint/CDC/RDC

Synthesis & RTL Signoff

Clock/Reset Architecture

RTL Quality Reviews

Automation (Python/TCL/Perl)

Job description

Hiring Design Engineer for Product based company (RTL Design & Quality Ownership)
We're looking for a highly motivated Design Engineer with 4-6 years of experience in RTL design, subsystem integration, and silicon-quality signoff.

Key Skills

• Verilog/SystemVerilog RTL Design
• IP/Subsystem/SoC Integration
• AMBA Protocols (AXI4, AXI4-Lite, AHB, APB)
• Lint, CDC, RDC Closure
• Synthesis & RTL Signoff
• Clock/Reset Architecture
• RTL Quality Reviews & Handoff Readiness
• Python/TCL/Perl Automation (preferred)

Responsibilities

• Develop high-quality synthesizable RTL
• Drive IP and subsystem integration
• Own RTL quality from development to handoff
• Drive closure of Lint, CDC, RDC, X-propagation, and synthesis issues
• Ensure clean signoff and production-ready RTL
• Improve RTL development methodologies through automation