Senior Principal Design Verification Engineer (PCIe Gen7.0 / Gen6.0 / Gen 5.0)

Mulya Technologies; Bengaluru; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

Join a leading company as a Design Verification Engineer to enhance performance and scalability in distributed computing systems. This role involves verifying large-scale networking and computing chips, ensuring high coverage and performance through collaboration and advanced techniques.

Qualifications

• Minimum 15-20 years experience with BSEE/CE or 12-20 years with MSEE/CE.
• Experience in high-performance networking or computing chips.

Responsibilities

• Collaborate with architects to develop comprehensive tests.
• Define and implement infrastructure for HW/SW co-simulation.
• Execute verification strategies to ensure specifications are met.

Skills

RTL verification

UVM

SystemVerilog

Python

C/C++

Education

BSEE

MSEE

Job description

9 hours ago Be among the first 25 applicants

Get AI-powered advice on this job and more exclusive features.

Direct message the job poster from Mulya Technologies

Founder @ Mulya - Ranked as the most admirable partner for Intel - India (2021)

Company Background

We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software, called the Accelerated Compute Fabric. Founded and led by an executive team from top semiconductor and distributed systems companies, we stand out with a strong engineering pedigree, proven track record, and significant investor support. Our approach aims to solve I/O bottlenecks in distributed AI and accelerated compute clusters, unleashing the next generation of computing fabrics.

Summary

Join an ambitious, experienced team as a design verification engineer to build groundbreaking products that enhance performance and scalability in distributed computing systems, addressing key infrastructure challenges.

We seek talented, motivated candidates experienced in designing and verifying large-scale networking and computing chips, eager to grow in a dynamic startup environment. The role covers the full chip development lifecycle, from microarchitecture to post-silicon testing.

Roles and Responsibilities

• Collaborate with hardware and software architects to develop comprehensive tests achieving high coverage.
• Apply advanced verification techniques to meet demanding scale and performance requirements.
• Define and implement infrastructure for HW/SW co-simulation.
• Execute verification strategies to ensure prototype meets specifications at device and system levels.
• Build infrastructure and tests compatible with ASIC and FPGA platforms.

Skills/Qualifications

• Proven experience verifying RTL designs for high-performance networking or computing chips (e.g., NICs, Smart-NICs, DPUs, accelerators, switches) in advanced silicon geometries.
• Deep knowledge of full chip verification and infrastructure development.
• Strong understanding of UVM, SystemVerilog, and scripting languages like Python.
• Experience with C/C++ and software engineering principles is highly desirable.
• Minimum BSEE/CE with 15-20 years or MSEE/CE with 12-20 years of industry experience.
• Track record of successful product design and high-volume shipping.

Contact:

"Mining The Knowledge Community"

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Research, Design, and Engineering

Industries

• Computer Hardware Manufacturing, Semiconductor Manufacturing, Software Development

Referrals increase your chances of interviewing at Mulya Technologies by 2x

Get notified about new Design Verification Engineer jobs in Greater Bengaluru Area.