Principal Physical Design Engineer

Mulya Technologies

Hyderabad

On-site

INR 7,005,253 - 10,507,880

Full time

14 days+

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Job summary

Join Mulya Technologies as a Principal Physical Design Engineer, where you'll work with a team of experts to revolutionize distributed computing infrastructure. This role involves the physical implementation of semiconductor products, requiring extensive experience and knowledge in CAD tools and physical design workflows.

Qualifications

15+ years experience with BSEE/CE or 12+ years with MSEE/CE.
Proven track record in high-performance network switching/routing.
Deep experience with CAD tools for physical design workflows.

Responsibilities

Build and support the CAD tool flow for physical implementation.
Define and construct major physical structures like clock and power delivery.
Interface with foundry and library partners on IP and process technology.

Skills

Physical implementation

CAD tools

SystemVerilog

Python

Perl

Circuit analysis

Education

BSEE/CE

MSEE/CE

Tools

Cadence Genus

Innovus

Synopsys ICC2

PrimeTime SI

Calibre

Job description

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Founder @ Mulya - Ranked as the most admirable partner for Intel -India (in 2021)

Principal Physical Design Engineer

PrincipalPhysical Design Engineer

Company Background

We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic.

Summary

Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers.

We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout.

Roles and Responsibilities

Build and support the CAD tool flow for physical implementation in a cloud-first development environment.
Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders.
Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies.
Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout.
Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff.

Skills/Qualifications:

Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes.
Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre.
Strong familiarity with various analysis tools such as Redhawk, Voltus.
Experience with circuit analysis using HSPICE is a plus.
Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages.
Minimum BSEE/CE + 15 years or MSEE/CE + 12 years experience.
Proven track record of execution on products which have shipped in high-volume.

Contact:

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Seniority level