Principal Physical Design Engineer

Mulya Technologies

Bengaluru Urban

On-site

INR 8,756,567 - 13,134,850

Full time

14 days+

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Job summary

Join a leading startup as a Principal Physical Design Engineer, where you will work with a talented team to revolutionize distributed computing infrastructure. This role offers the chance to implement large-scale semiconductor products in a fast-paced environment, leveraging your extensive experience in physical design and CAD tools.

Qualifications

15+ years of industry experience with a track record of shipped high-volume products.
Deep familiarity with CAD tools and physical implementation of high-performance network fabrics.
Expertise in SystemVerilog and scripting languages like Perl or Python.

Responsibilities

Build and support the CAD tool flow for physical implementation.
Collaborate on chip-level floorplanning and block partitioning.
Execute physical implementation tasks including synthesis and timing closure.

Skills

Physical implementation

CAD tools

SystemVerilog

Scripting languages

Circuit analysis

Education

BSEE/CE

MSEE/CE

Tools

Cadence Genus

Innovus

Synopsys ICC2

Tempus

PrimeTime

StarRC

Calibre

Redhawk

Voltus

HSPICE

Job description

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Founder @ Mulya - Ranked as the most admirable partner for Intel -India (in 2021)

Principal Physical Design Engineer

Company Background

We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful track record in early-stage investments. Our diverse team of chip/software/systems architects and developers excels in hardware/software solution co-design. We have built and delivered technologies that process over half of the world's global data center traffic.

Summary

Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our mission is to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You will have the opportunity to build groundbreaking products alongside talented hardware and software engineers, creating disruptive infrastructure solutions that delight customers.

We seek talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, eager to grow in a fast-paced startup environment. Candidates should have experience across the full chip development lifecycle, including CAD tool flow setup, floorplanning, block partitioning, power planning, clock network design, P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout.

Roles and Responsibilities

Build and support the CAD tool flow for physical implementation in a cloud-first environment.
Collaborate with architects and microarchitects on chip-level floorplanning and block partitioning, evaluating tradeoffs in functional partitioning, block size, and interface complexity.
Define and construct physical structures such as clock/reset architecture, power delivery network, and interconnect topologies.
Execute physical implementation tasks at block, cluster, and top levels, including synthesis, floorplanning, P+R, timing closure, physical verification, and tapeout.
Coordinate with foundry and library partners on IP and process technology issues, device models, and pre-tapeout signoff.

Skills/Qualifications:

Proven experience in physical implementation of large, high-performance network fabrics, NICs, CPUs, or GPUs in advanced silicon nodes.
Deep familiarity with CAD tools like Cadence Genus, Innovus, Synopsys ICC2, Tempus, PrimeTime, StarRC, Calibre, etc.
Experience with analysis tools such as Redhawk and Voltus.
Circuit analysis experience with HSPICE is a plus.
Expertise in SystemVerilog, scripting languages like Perl or Python.
Minimum BSEE/CE + 15 years or MSEE/CE + 12 years of industry experience.
Track record of shipped high-volume products.

Contact:

"Mining The Knowledge Community"

Seniority level