Principal Design Verification Engineer (Switching , Data path)

Mulya Technologies; Bengaluru Urban; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

A leading company in AI compute systems is seeking a Principal Design Verification Engineer to join their innovative team. The role involves collaborating with hardware and software architects, implementing verification techniques for cutting-edge networking chips, and contributing throughout the chip development lifecycle. Candidates should have extensive experience in verifying RTL designs and a strong educational background in Electrical or Computer Engineering.

Qualifications

• 12-17 years experience for BSEE/CE or 12-15 years for MSEE/CE.
• Proven experience in high-performance networking or computing chips.
• Track record of delivering high-volume shipped products.

Responsibilities

• Collaborate with architects to convert product specifications into tests.
• Implement verification techniques for high-performance devices.
• Build infrastructure compatible with ASIC and FPGA platforms.

Skills

Verifying RTL designs

DDR5 memory technology

Full-chip verification

UVM constructs

SystemVerilog

Python

C/C++

Education

BSEE/CE or MSEE/CE

Job description

Principal Design Verification Engineer (Switching, Data Path)

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Founder @ Mulya - Ranked as the most admirable partner for Intel - India (2021)

India

Company Background

We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software, which we call the Accelerated Compute Fabric. Founded and led by an executive team from top semiconductor and distributed systems/software companies, we stand out with a strong engineering pedigree, a proven track record, and significant investor support. Our approach aims to solve I/O bottlenecks in distributed AI and compute clusters, revolutionizing next-gen computing fabrics.

Summary

Join an ambitious team of silicon and distributed systems experts as a design verification engineer. You will help build groundbreaking products that enhance performance and scalability of distributed computing systems and address infrastructure challenges.

We seek talented, motivated candidates with experience in designing and verifying large-scale networking and computing chips, eager to grow in a dynamic startup environment. Candidates should be capable of contributing throughout the chip development lifecycle, from microarchitecture to post-silicon testing.

Roles and Responsibilities

• Collaborate with distributed systems hardware and software architects to convert product specifications into comprehensive tests with high coverage.
• Implement state-of-the-art verification techniques for complex, high-performance devices.
• Define and develop infrastructure for HW/SW co-simulation.
• Ensure prototypes meet device and system-level specifications through verification strategies.
• Build infrastructure and tests compatible with ASIC and FPGA platforms.

Skills/Qualifications

• Proven experience verifying RTL designs for high-performance networking or computing chips (e.g., NICs, Smart-NICs, DPUs, accelerators, switches) in advanced silicon processes.
• Experience with DDR5 memory technology.
• Deep expertise in full-chip verification and infrastructure development.
• Strong knowledge of UVM constructs, components, and practices.
• Proficiency in SystemVerilog, Python, or similar scripting languages.
• Experience with C/C++ and software engineering principles is a plus.
• Minimum BSEE/CE with 12-17 years or MSEE/CE with 12-15 years of relevant experience.
• Track record of delivering high-volume shipped products with quality.

Contact:

"Mining The Knowledge Community"

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Research, Design, and Engineering

Industries

• Computer Hardware Manufacturing, Semiconductor Manufacturing, Network Security