Principal Design Verification Engineer

Mulya Technologies; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

A semiconductor company is seeking a Principal / Staff Design Verification Engineer to apply uniform standards in verification methodology and work closely with design teams. The ideal candidate will have over 10 years of experience in silicon ICs and strong proficiency in UVM and Verilog. Responsibilities include overseeing debugging and ensuring design requirements for projects are met. This full-time role offers a mid-senior level position in Bengaluru, India.

Qualifications

• 10+ years of industry experience in silicon ICs.
• Full-chip verification experience.
• Experience leading single projects.

Responsibilities

• Responsible for verification methodology and standards.
• Work with design teams to meet project requirements.
• Oversee debugging problems in real time.

Skills

UVM

Verilog

C/C++ programming

Debugging

Scripting in Perl/Python

Education

BS or MS in Computer Science or Electrical Engineering

Tools

Simulation tools

Formality

Job description

4 hours ago Be among the first 25 applicants

Get AI-powered advice on this job and more exclusive features.

Direct message the job poster from Mulya Technologies

Overview

Principal / Staff Design Verification Engineer

We are an innovative enterprise that designs, develops, and delivers System-on-Chip products to customers worldwide. The company focuses on AR/VR, imaging, networking, storage, and other dynamic technologies that drive today’s leading-edge applications. Founded in 2015, we are headquartered in Japan, with offices in Japan, Asia, United States and Europe to lead product development and sales activities.

Responsibilities

• Responsible for all aspects of verification methodology and for ensuring the application of uniform standards and adoption of best practices.
• Work and liaison with other Design Verification teams within customer sites to identify holes in the design verification flow and implement corrective actions.
• Verify ASIC designs, including design verification – implement test benches in UVM and SystemVerilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage, debug failures and provide feedback to the design team.
• Oversee and complete debugging problems and troubleshooting in Real Time, including debugging designs for high throughput, low latency of pipeline and dynamic power management at full system level.
• Setup verification regression suites at RTL level and corresponding netlist level after synthesis to test corner-case conditions.
• Work closely with design teams to ensure the company meets design requirements for projects (review specifications, understand chip architecture, develop tests & coverage plans, define methodology & test benches).
• Work with the Custom SoC department to provide excellent customer service to clients and projects, supporting and driving timely and accurate deliverables within schedule.

Qualifications

• BS or MS in Computer Science or Electrical Engineering; 10+ years of industry experience bringing silicon ICs into high-volume production.
• Strong experience with UVM; full-chip verification experience.
• Experience leading a single project and knowledge of industry standard interfaces; extensive familiarity with Verilog, simulation tools, and ability to debug and troubleshoot in real time.
• Solid knowledge of ARMv8, interconnect, memory coherence and memory architecture.
• Familiarity with Formality and popular verification tools; topics include IP validation, gate-level verification, FPGA validation, emulation, silicon validation, reference board bring-up, silicon bring-up, DFx, low power verification.
• Expertise in writing Perl / Python, awk, sed and other scripts to automate verification tasks for CPU and all chip peripherals (USB, PCIe, MIPI, SDIO, PCIe & DDR controllers); experience with ASIC design and verification flow including RTL, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation.
• Experience with low-level programming (C/C++); scripting in Perl, Python, Tcl, C/C++.
• Functional understanding of constrained random verification, functional and code coverage; low power verification UPF.
• Team player with excellent communication skills and the desire to take on diverse challenges.

Other Qualifications

• Good knowledge of low power camera and imaging systems is a plus.
• Experience with formal verification tools; familiarity with ARM architecture; scripting/programming with Perl/Python, Tcl, C/C++.
• Mining The Knowledge Community

Details

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Job function: Design, Research, and Engineering
• Industries: Semiconductor Manufacturing, Computer Hardware Manufacturing, and Computer and Network Security

Referrals increase your chances of interviewing at Mulya Technologies by 2x

Sign in to set job alerts for “Design Verification Engineer” roles.

Related roles

• ASIC Design Engineer - Security Subsystem
• Silicon Design Verification Engineer, TPU, Google Cloud

We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.