Principal Design Verification Engineer (DDR7 / DDR6 / DDR5)

Mulya Technologies; Bengaluru Urban; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Join a leading technology company as a Design Verification Engineer, where you will contribute to groundbreaking advancements in AI compute systems. Your role will involve verifying high-performance networking chips and ensuring they meet rigorous specifications, all within a dynamic startup environment.

Qualifications

• Minimum 12-17 years of experience for BSEE/CE or 12-15 years for MSEE/CE.
• Proven experience in high-performance networking or computing chips.

Responsibilities

• Collaborate with architects to develop comprehensive tests.
• Implement advanced verification techniques.
• Design infrastructure for HW/SW co-simulation.

Skills

Verification of networking chips

DDR5 memory

Full chip verification

UVM

SystemVerilog

Python

C/C++

Education

BSEE/CE or MSEE/CE

Job description

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Founder @ Mulya - Ranked as the most admirable partner for Intel - India (in 2021)

India

Company Background

We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software, called the Accelerated Compute Fabric. Founded and led by an executive team from top semiconductor and distributed systems/software companies, we are distinguished by our strong engineering pedigree, proven track record, and significant investor support. Our approach aims to solve I/O bottlenecks in distributed AI and accelerated compute clusters, unleashing the next generation of computing fabrics.

Summary

Join our ambitious team as a design verification engineer, where you'll help build a groundbreaking product that enhances performance and scalability in distributed computing systems, addressing critical infrastructure challenges.

We seek talented, motivated candidates with experience in designing and verifying large-scale networking and computing chips, eager to grow in a fast-paced startup environment. Responsibilities include full chip development lifecycle, from microarchitecture to post-silicon testing.

Roles and Responsibilities

• Collaborate with hardware and software architects to develop comprehensive tests achieving high coverage.
• Implement advanced verification techniques to meet demanding performance requirements.
• Design infrastructure for HW/SW co-simulation.
• Ensure prototype meets device and system-level specifications.
• Build infrastructure and tests adaptable across ASIC and FPGA platforms.

Skills/Qualifications

• Proven experience verifying high-performance networking or computing chips, such as NICs, Smart-NICs, DPUs, accelerators, or switches, in advanced silicon geometries.
• Experience with DDR5 memory.
• Deep knowledge of full chip verification and infrastructure development.
• Expertise in UVM, SystemVerilog, and scripting languages like Python.
• Knowledge of C/C++ and software engineering principles is desirable.
• Minimum BSEE/CE with 12-17 years or MSEE/CE with 12-15 years of experience.
• Track record of delivering high-volume shipped products.

Contact:

"Mining The Knowledge Community"

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Research, Design, and Engineering

Industries

• Computer Hardware Manufacturing
• Semiconductor Manufacturing
• Software Development

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