Senior Physical Design Engineer

Bitsilica; Bengaluru; On-site; INR 2,500,000 - 4,200,000; Full time

Job summary

Bitsilica is seeking a Senior Physical Design Engineer in Bengaluru to lead end-to-end SoC implementation on advanced nodes (7nm/5nm/3nm). You will work with synthesis, STA, and DFT teams to deliver GDSII with strong PPA targets and robust power delivery.

You will own the physical design flow from floorplanning to routing, perform STA timing closure, handle DRC/LVS/antenna checks, and optimize for area and power while collaborating with RTL/DFT teams to meet project milestones.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field.
• Experience on advanced nodes (7nm/5nm/3nm).
• Proficiency with industry tools (Innovus/ICC2, Calibre/ICV).

Responsibilities

• Netlist-to-GDSII Flow: Execute the complete physical design flow, including Floorplanning, Placement, CTS, and Routing.
• Timing Closure: Perform Static Timing Analysis and timing closure across corners and modes.
• Physical Verification: Own and resolve DRC, LVS, ERC, and Antenna violations using industry tools.
• Power Analysis: Conduct IR drop and EM analysis to ensure robust power delivery.
• Optimization: Implement area reduction techniques and low-power design methodologies (UPF/CPF).
• Collaboration: Interface with RTL and DFT teams to resolve design hurdles and provide feedback on physical constraints.

Skills

Hierarchical design

Multi-voltage domains

Congestion management

Scripting: Tcl/Python/Perl

Education

Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field

Tools

Innovus Cadence

ICC2 Synopsys

Calibre

Assura

ICV

Tcl/Python scripting

Job description

As a Senior Physical Design Engineer, you will be responsible for the end-to-end implementation of complex SoCs at advanced process nodes (e.g., 7nm, 5nm, and below). You will work closely with the synthesis, STA, and DFT teams to deliver high-quality GDSII, ensuring all PPA (Power, Performance, Area) targets are met.

Responsibilities

• Netlist-to-GDSII Flow: Execute the complete physical design flow, including Floorplanning, Placement, Clock Tree Synthesis (CTS), and Routing.
• Timing Closure: Perform Static Timing Analysis (STA) and timing closure across all corners and modes (setup, hold, recovery, removal).
• Physical Verification: Own and resolve DRC, LVS, ERC, and Antenna violations using industry-standard tools.
• Power Analysis: Conduct IR drop analysis (Static and Dynamic) and EM (Electromigration) analysis to ensure robust power delivery.
• Optimization: Implement area reduction techniques and low-power design methodologies (UPF/CPF).
• Collaboration: Interface with the RTL and DFT teams to resolve design hurdles and provide feedback on physical constraints.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field.

Required Skills

• EDA Tools: Proficiency in industry-leading tools such as Innovus (Cadence) or ICC2 (Synopsys).
• Verification Tools: Hands-on experience with Calibre, Assura, or ICV.
• Methodology: Strong understanding of hierarchical design, multi-voltage domains, and congestion management.
• Nodes: Experience working on advanced process nodes (7nm/5nm/3nm).
• Scripting: Ability to automate tasks using Tcl, Perl, or Python.

Preferred Skills

• Strong analytical and problem-solving skills.
• Excellent communication skills for cross-functional team coordination.