Physical Design

Semi Leaf; Bengaluru; On-site; USD 900 - 1,687; Full time

Job summary

An innovative firm is seeking a highly skilled Physical Design Engineer with extensive experience in Netlist2GDSII implementation and advanced design methodologies. This role involves working with cutting-edge technologies in the semiconductor industry, focusing on floorplanning, power grid design, and chip finishing for sub-micron technology nodes. The ideal candidate will have a strong background in automation using Tcl/Tk/Perl and hands-on experience with industry-standard PnR suites. Join a forward-thinking company where your expertise will contribute to groundbreaking projects and drive efficiency in design processes.

Qualifications

• 5-15 years of experience in Physical Design and methodologies.
• Hands-on experience with tools like Synopsys and Cadence.

Skills

Netlist2GDSII Implementation

Tcl/Tk/Perl Programming

PnR Suite (Synopsys/Cadence)

Static Timing Analysis (PrimeTime - SI)

EM/IR-Drop Analysis

Physical Verification (Calibre)

SOC Integration

Low Power Design

High Speed Design

Advanced Physical Verification Techniques

Job description

Experience:

5-15 years

Skills Required:

1. In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes.
2. Experience on programming in Tcl/Tk/Perl to automate design processes and improve efficiency.
3. Hands-on experience on PnR Suite from Synopsys/Cadence (Innovus, ICC2).
4. Strong experience on Static Timing Analysis (PrimeTime - SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre).
5. Understanding of practical application of methodologies and Physical Design Tools, Flow Automation and Improvements.
6. Experience in complex SOC integration, Low Power and High Speed Design, and Advanced Physical Verification Techniques.