Senior Physical Design Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 2,000,000 - 3,200,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru seeks an experienced Senior Physical Design Engineer with 5+ years of hands-on expertise in RTL-to-GDSII flow, timing closure, PPA optimization, and physical verification. You will own block-level and full-chip implementation, drive floorplanning, CTS, routing, and signoff, and mentor junior PD engineers while coordinating with RTL, Synthesis, and PV teams.

The role requires leadership in physical design activities and strong knowledge of VLSI, CMOS, and

Qualifications

• 5+ years of experience in physical design
• Strong knowledge of VLSI, CMOS, and semiconductor design
• Experience in block-level and full-chip implementation
• Experience leading physical design activities preferred

Responsibilities

• Own the RTL-to-GDSII / Netlist-to-GDSII flow.
• Drive floorplanning, power planning, placement, CTS, routing, and signoff.
• Lead timing closure across multiple modes and corners.
• Analyze and resolve setup, hold, congestion, and routing issues.
• Drive PPA optimization at block and full-chip levels.
• Optimize floorplan, placement, clock architecture, and routing for performance and area.
• Perform CTS optimization and clock skew/latency management.
• Debug and close DRC, LVS, antenna, EM/IR, and signal-integrity issues.
• Perform timing, physical, and functional ECO implementation.
• Work closely with RTL, Synthesis, STA, PV, DFT, and methodology teams.
• Mentor junior Physical Design engineers and drive technical execution.
• Support final signoff and tape-out activities.

Skills

Leadership

Timing closure

Block/Full-chip design

Advanced nodes experience

Education

BE/B.Tech/M.E./M.Tech in ECE/EEE/VLSI or related field

Tools

RTL-to-GDSII flow

Floorplanning

Power/Clock planning

CTS / Routing

Signoff

DRC/LVS/EM-IR

Job description

Senior Physical Design Engineer - 5+ Years

Job Summary

We are looking for an experienced Senior Physical Design Engineer with 5+ years of hands-on experience in advanced-node physical implementation. The candidate should have strong expertise in complete RTL-to-GDSII flow, timing closure, PPA optimization, physical verification, and block/top-level implementation.

Experience

• 5+ years of experience in Physical Design
• Strong experience with advanced technology nodes
• Experience in block-level and/or full-chip implementation
• Experience in leading physical design activities is preferred

Education

• B.E./B.Tech/M.E./M.Tech in Electronics & Communication Engineering (ECE), Electrical & Electronics Engineering (EEE), Electronics Engineering, VLSI, or a related field.
• Strong knowledge of VLSI, Digital Electronics, CMOS, Semiconductor Design, and Physical Design methodologies.
• M.E./M.Tech in VLSI or Microelectronics is an added advantage.

Key Responsibilities

• Own and execute the complete RTL-to-GDSII / Netlist-to-GDSII flow.
• Drive floorplanning, power planning, placement, CTS, routing, and signoff.
• Lead timing closure across multiple modes and corners.
• Analyze and resolve complex setup, hold, congestion, and routing issues.
• Drive PPA optimization at block and full-chip levels.
• Optimize floorplan, placement, clock architecture, and routing for performance and area.
• Perform CTS optimization and clock skew/latency management.
• Debug and close DRC, LVS, antenna, EM/IR, and signal-integrity issues.
• Perform timing, physical, and functional ECO implementation.
• Work closely with RTL, Synthesis, STA, PV, DFT, and methodology teams.
• Mentor junior Physical Design engineers and drive technical execution.
• Support final signoff and tape-out activities.

Most Important Technical Skills

• Power Grid Design
• Placement Optimization
• Clock Tree Synthesis & Optimization
• CTS / CCD
• Global & Detailed Routing
• Multi-mode Multi-corner (MMMC) Timing Closure