Physical Design Engineer

Serendipity Corporate Services; Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Serendipity Corporate Services in Bengaluru, India seeks a senior RTL-to-GDSII physical design engineer to lead the complete design flow from RTL to GDSII. You will drive floorplanning, CTS, routing, timing analysis and design sign-off, collaborating with RTL, synthesis, STA, DFT and verification teams to resolve issues and optimize performance, power and area.

The ideal candidate has 6+ years of relevant experience in chipset/SoC physical design, DRC/LVS, EM checks, and antenna checks, with a

Qualifications

• Work experience 6+ years in RTL-to-GDSII physical design.

Responsibilities

• Perform complete RTL-to-GDSII physical design flow.
• Execute floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Perform timing analysis and optimization for setup and hold violations.
• Analyze and resolve congestion, timing, power, and area issues.
• Perform static timing analysis (STA) and timing closure.
• Work on clock tree optimization and CTS/CCOpt activities.
• Perform placement optimization and routing using industry-standard EDA tools.
• Analyze and resolve DRC, LVS, antenna, IR drop, and electromigration (EM) issues.
• Support ECO implementation and design optimization.
• Work with RTL, synthesis, STA, DFT, and verification teams to resolve design issues.
• Generate and review physical design reports and ensure design quality.
• Participate in design sign-off activities and ensure compliance with project requirements.
• Contribute to improving physical design methodologies, automation, and flow efficiency.

Job description

Work Experience Required- 6+ Year.

Key Responsibilities

• Perform complete RTL-to-GDSII physical design flow.
• Execute floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Perform timing analysis and optimization for setup and hold violations.
• Analyze and resolve congestion, timing, power, and area issues.
• Perform static timing analysis (STA) and timing closure.
• Work on clock tree optimization and CTS/CCOpt activities.
• Perform placement optimization and routing using industry-standard EDA tools.
• Analyze and resolve DRC, LVS, antenna, IR drop, and electromigration (EM) issues.
• Support ECO implementation and design optimization.
• Work with RTL, synthesis, STA, DFT, and verification teams to resolve design issues.
• Generate and review physical design reports and ensure design quality.
• Participate in design sign-off activities and ensure compliance with project requirements.
• Contribute to improving physical design methodologies, automation, and flow efficiency.