Lead Physical Design Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 3,500,000 - 6,500,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru, India, seeks a Lead Physical Design Engineer to own full-chip physical design from netlist to GDSII, including floorplanning, placement, CTS, routing and physical optimization. You will drive timing closure across hierarchical designs and ECO implementations, with strong Cadence Innovus expertise to optimize and deliver signoff-ready results.

The role requires hands-on leadership in floorplanning, power planning, routing and ECOs, plus collaboration

Qualifications

• 6–12 years of hands-on experience in Physical Design/Physical Implementation.
• Strong full-chip Physical Design experience with ownership of large, complex SoCs.
• Expert-level hands-on experience with Cadence Innovus.
• Solid knowledge of floorplanning, placement, CTS, routing, optimization and ECO flows.
• Proficiency in Tcl scripting; Python/Perl scripting is a plus.
• Strong debugging, problem-solving and cross-functional collaboration skills.

Responsibilities

• Own full-chip physical design from netlist-to-GDSII, including floorplanning, placement, CTS, routing and physical optimization.
• Drive timing closure across hierarchical/full-chip designs, including setup/hold analysis and ECO implementation.
• Strong hands-on expertise with Cadence Innovus for implementation and optimization.
• Perform floorplan, power planning, placement, CTS, routing and congestion optimization.
• Debug and resolve timing, congestion, DRC, LVS and routing issues.
• Work closely with STA, RTL, synthesis, DFT, power and signoff teams to achieve design closure.
• Execute MMMC-based implementation and optimize designs across multiple PVT scenarios.
• Drive physical and timing ECOs through final signoff.
• Analyze and improve PPA while maintaining design robustness and signoff quality.
• Contribute to flow improvement, automation and methodology development using Tcl/Python/Perl.

Skills

Full-chip PD

Cadence Innovus

Tcl scripting

Python scripting

Problem-solving

Tools

Cadence Innovus

Job description

We are looking for a Lead Physical Design Engineer with strong hands-on experience in full-chip Physical Design and Cadence Innovus. The role involves owning critical stages of the physical implementation flow and driving design closure across PPA, timing, power, and physical signoff.

Key Responsibilities

• Own full-chip physical design from netlist-to-GDSII, including floorplanning, placement, CTS, routing and physical optimization.
• Drive timing closure across hierarchical/full-chip designs, including setup/hold analysis and ECO implementation.
• Strong hands-on expertise with Cadence Innovus for implementation and optimization.
• Perform floorplan, power planning, placement, CTS, routing and congestion optimization.
• Debug and resolve timing, congestion, DRC, LVS and routing issues.
• Work closely with STA, RTL, synthesis, DFT, power and signoff teams to achieve design closure.
• Execute MMMC-based implementation and optimize designs across multiple PVT scenarios.
• Drive physical and timing ECOs through final signoff.
• Analyze and improve PPA while maintaining design robustness and signoff quality.
• Contribute to flow improvement, automation and methodology development using Tcl/Python/Perl.

Required Qualifications

• 6–12 years of hands-on experience in Physical Design/Physical Implementation.
• Strong full-chip Physical Design experience with ownership of large and complex SoCs.
• Expert-level hands-on experience with Cadence Innovus.
• Strong understanding of floorplanning, placement, CTS, routing, optimization and ECO flows.
• Solid knowledge of STA, MMMC, timing constraints and timing closure.
• Experience with congestion, IR/EM, DRC/LVS and physical signoff.
• Strong understanding of low‑power design concepts and multi‑voltage implementation is preferred.
• Proficiency in Tcl scripting; Python/Perl scripting is a plus.
• Strong debugging, problem-solving and cross-functional collaboration skills.

Preferred

• Experience on advanced-node SoC designs.
• Experience driving full-chip PPA and timing closure.
• Exposure to physical signoff tools and methodologies.
• Experience working with high-performance CPU, AI/ML, networking or complex SoC designs.