Senior Technical Architect - Physical Design

Quest Global; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

A leading semiconductor company in Bengaluru is looking for a Senior Technical Architect specialized in physical design to lead turnkey SoC projects. The ideal candidate will possess extensive hands-on experience in RTL-to-GDS implementation, manage complex designs, and drive technical excellence. Responsibilities include mentoring teams, developing design flows, and interfacing with customers. Applicants should have 15+ years in physical design, strong skills in scripting, and familiarity with tools like Synopsys and Cadence.

Qualifications

• 15–25 years of hands‑on experience in physical design implementation.
• Deep expertise in PD tools and flows covering synthesis, STA, PNR, signoff domain.
• Strong scripting skills in TCL and Python.

Responsibilities

• Define and drive end‑to‑end RTL‑to‑GDSII flows for customer‑specific projects.
• Mentor teams on advanced technology node implementation.
• Own and refine PD reference flows and automation scripts.

Skills

Physical design implementation

RTL2GDS implementation

Low power flows

TCL scripting

Python scripting

Tools

Synopsys Fusion Compiler

Cadence Innovus

Ansys RedHawk

Job description

Senior Technical Architect - Physical Design

Job Title: Senior Technical Architect - Physical Design

Experience: 15 - 22 Years

Role Summary:

This is a deep technical leadership role focused on architecting and guiding turnkey SoC physical design projects. The ideal candidate will have extensive hands‑on expertise in RTL2GDS implementation at advanced nodes (3nm/5nm), be customer‑facing, and capable of owning project methodology, technical quality, and solution engineering end to end.

Key Responsibilities

Turnkey Delivery Leadership

• Define and drive end‑to‑end RTL‑to‑GDSII flows, tailored for customer‑specific technology, tools, and deliverables.
• Lead complex top‑level and hierarchical SoC designs, ensuring quality and signoff compliance.
• Guide floorplan strategy, power planning, PPA closure, IR/EM signoff, and integration challenges.
• Understand customer requirements and provide technical solutions, execution strategies, and staffing recommendations.
• Interface with customer architects and stakeholders for reviews, issue resolution, and milestones.

Technical Mentorship

• Mentor physical design teams on advanced technology node implementation, complex SoC partitioning, and tool optimizations.
• Review block‑level signoff issues, methodology gaps, and drive technical excellence across projects.

Flow Development and Innovation

• Own and refine PD reference flows, checklists, automation scripts, and ECO methodologies.
• Drive low power implementation (UPF), hierarchical signoff closure, and flow correlation across synthesis, STA, and physical domains.

Skills & Experience Required

• 15–25 years of hands‑on experience in physical design implementation. Lead multiple complex design tapeouts on advanced tech nodes.
• Deep expertise in PD tools and flows covering synthesis, STA, PNR, signoff domain. Eg. Synopsys Fusion Compiler, ICC2, PrimeTime, ICV, Cadence Innovus/Tempus, Ansys RedHawk, Caliber, UPF, CLP etc.
• Strong grasp of low power flows, multi‑voltage/multi‑Vt, UPF, and power intent checks.
• Experience in managing or technically driving multiple successful tapeouts (including full‑chip or subsystems).
• Strong scripting in TCL, Python, and ability to drive flow optimizations.
• Excellent problem‑solving, debugging, and documentation skills.
• Prior customer‑facing or solution architect experience preferred.

Seniority level

Director

Employment type

Full‑time

Job function

Design, Engineering, and Management

Industries

Semiconductor Manufacturing, Computer Hardware Manufacturing, and Computers and Electronics Manufacturing