Lead/Senior Memory Layout engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd in Bengaluru, India seeks an experienced Memory Layout Engineer to design layouts for building blocks like Bit Cell Arrays, Row/Column Decoders, Sense Amplifiers, and I/O Blocks, and to integrate top-level memory layouts.

Shaping layouts for advanced nodes (2nm/3nm/5nm) with a strong focus on physical verification (DRC/LVS), DFM/DFY compliance, and power/signal integrity. scripting skills in PERL, Shell, TCL, or SKILL are a plus.

Qualifications

• Strong hands-on experience in Memory Layout for advanced technology nodes.
• Expertise in TSMC and/or other process technologies with lower nodes (2nm/3nm/5nm).
• Solid understanding of physical verification, layout methodologies, and semiconductor design flows.
• Scripting knowledge is an added advantage.

Responsibilities

• Design memory layouts for building blocks, including Bit Cell Arrays, Row Decoders, Column Decoders, Sense Amplifiers, and I/O Blocks.
• Integrate top-level memory layouts.
• Perform physical verification using DRC and LVS.
• Ensure layouts comply with DFM and DFY requirements.
• Analyze layouts for power integrity and signal integrity.
• Develop and maintain automation scripts using PERL, Shell, TCL, or SKILL.

Skills

Memory Layout

Physical verification

DFM/DFY awareness

Scripting knowledge

Tools

PERL

Shell

TCL

SKILL

Job description

We're looking for experienced Memory Layout Engineers to join our team and work on cutting-edge semiconductor technologies.

Experience: 4+ Years

Key Responsibilities:

• Design memory layouts for various building blocks, including:
• Bit Cell Arrays ,Row Decoders, Column Decoders, Sense Amplifiers, Input/Output (I/O) Blocks
• Integrate top-level memory layouts.
• Perform physical verification using DRC and LVS.
• Ensure layouts comply with Design for Manufacturability (DFM) and Design for Yield (DFY) requirements.
• Analyze layouts for power integrity and signal integrity.
• Develop and maintain automation scripts using PERL, Shell, TCL, or SKILL.

Required Skills:

Strong hands-on experience in Memory Layout for advanced technology nodes.

Expertise in TSMC and/or other process technologies with lower nodes (2nm/3nm/5nm).

Solid understanding of physical verification, layout methodologies, and semiconductor design flows.

Scripting knowledge is an added advantage.