Memory Layout Engineer

Capgemini Engineering; Bengaluru; On-site; INR 1,500,000 - 3,000,000; Full time

Job summary

Capgemini Engineering is seeking a Memory Layout Engineer in Bengaluru to design and develop memory blocks for ICs. You will contribute to bit cell arrays, decoders, and I/O blocks while meeting performance, power, and area targets.

The role requires 3–7 years of memory layout experience, proficiency with Cadence Virtuoso and Assura, and a solid understanding of SRAM architectures, DFM/DFY concepts, and reliability considerations. scripting skills (Perl/Shell/TCL/Skill) are a plus.

Qualifications

• Bachelors in Electrical or Computer Engineering.
• 3–5 years in memory layout design.
• Experience with Cadence Virtuoso and Assura.
• Knowledge of SRAM design and memory sub-blocks.
• DFM/DFY concepts knowledge.

Responsibilities

• Design memory layouts for building blocks including bit cell array, row decoder, and I/O blocks.
• Integrate top-level memory blocks.
• Perform physical verification using DRC and LVS.
• Ensure layouts meet DFM and DFY requirements.
• Analyze layouts for power and signal integrity issues.
• May involve scripting using Perl, Shell, TCL, or Skill.

Skills

Memory layout

DRC/LVS

Scripting: Perl/TCL

Education

Bachelors in Electrical/Computer Engineering

Tools

Cadence Virtuoso

Assura

Job description

This role is for a Memory Layout Engineer with 3-7 years of experience to design and develop memory blocks for integrated circuits (ICs). You will be responsible for creating efficient memory layouts that meet performance, power, and area constraints.

Responsibilities:

• Design memory layouts for various building blocks including:
• Bit cell array
• Row decoder
• Input/Output (I/O) blocks
• Integrate top-level memory blocks
• Perform physical verification using tools like Design Rule Check (DRC) and Layout Versus Schematic (LVS)
• Ensure layouts meet Design for Manufacturability (DFM) and Design for Yield (DFY) requirements
• Analyze layouts for potential power and signal integrity issues
• May involve scripting using languages like PERL, Shell, TCL, or Skill

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
• 3-5 years of experience in memory layout design
• Proven experience with memory layout tools like Cadence Virtuoso and Assura
• Understanding of memory compiler architectures and sub-blocks
• Experience with low-power, high-performance, and high-density SRAM memory design (experience with different technology nodes is a plus)
• Knowledge of Design for Manufacturability (DFM) and Design for Yield (DFY) concepts
• Strong analytical and problem-solving skills
• Excellent communication and teamwork abilities

Preferred Skills:

• Experience with custom and compiler-based memory layout
• Experience with FinFET process technologies
• Experience with memory verification methodologies

Requirements added by the job poster

3+ years of work experience with SRAM

3+ years of work experience with Layout Design